International Business Machines Corporation

Daniel J Esteban

Claude R Galand

Larry D Larsen

Gardner D Jones, Jr

Jean E Menez

Jean-Francois Le Pennec

Patrick Michel

Daniel Mauduit

Lee S Rogers

Philippe Therias

Jean-Paul Beraud

Philippe Dalmas

Alain Croisier

The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of 'hot bits' existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent separation of these two instructions, interrupt protection is always provided for such sequences. Indirect branching is also accommodated by making available the contents of a common data bus to be placed in the instruction address register that would be branched to. The contents of the data bus depend upon the instruction which executes simultaneously with the branch instruction, i.e., that which is in the third phase in the pipeline. Interrupt protection is therefore required for these types of branching actions as well.

Branch control in a three phase pipelined signal processor

A terminal adapter for a telecommunication network having a receiver for multiple HDLC communication channels. The receiver includes a BCC calculator for computing and checking the validity of a received HDLC CNM frame. The terminal adapter further includes a device for detecting the reception of a specific CNM header included in a CNM frame on any of the HDLC communication channels and responsive to the detection for setting the BCC calculator to a predefined state. The latter state corresponds to the state of the BCC calculator after a computation of BCC for the specific CNM header. Therefore the BCC calculator can proceed with computation of said BCC for the CNM frame.

Terminal adapter having a multiple HDLC communication channels receiver

This processor is a single chip implementation of an architecture that is designed to expeditiously handle certain tasks commonly associated with signal processing. Sequential multiply and accumulate operations, in particular, can be accomplished quite efficiently. The processor is pipelined in two areas. Instructions are passed through a three phase pipeline and consist of fetch, decode and execute, while the multiplier utilizes a two phase pipeline. The data flow is parallel and of 16-bit width throughout. The instruction store is maintained separately from the data store and provisions are included for having the processor enabled to read and write its own instruction store. Some parallel or compound instructions are implemented to permit transfer actions such as storage or I/O to or from instruction registers to occur concurrently with a compute action in different segments of the data flow. The arithmetic capabilities of the processor include both the separate multiplier and a full arithmetic logic unit. Two DMA modes are permitted. Extensive diagnostic capabilities, some of which utilize the processor's ability to read and write its own instruction store, are also included.

Three phased pipelined signal processor

This improved speech signal Block Coded PCM (BCPCM) system reduces the number of bits allocated to transmitting the scale factor, thereby releasing bits for allocation to coding samples in the associated block of samples. The scale factor (c) is calculated for every 16 millisecond block of samples. However, the scale factor will be transmitted only once per 32 millisecond block if there is no significant difference between the two sequential values. The original speech signal is split into 16 frequency subbands, each subband initials sampled and 12-bit coded, then requantized in BCPCM at dynamically variable bit rates depending on the scale factor transmission rate.

Speech coding method and device for implementing the improved method

The improved multiplexer described herein uses split band encoding across a plurality of input ports to increase the statistical advantage for compression gains but does not require a large number of input ports to achieve its advantage.

Method and apparatus for efficient statistical multiplexing of voice and

A voice signal is transmitted digitally at reduced bit rate by use of data compression. The original frequency components of a telephone band width of the voice signal sampled at 8 KHz and quantized with 12 bits are transformed into three parameters: SIGNAL data representing adaptive quantization for lower frequency (300-800 Hz) sub-bands; COEF data representing pre-emphasized parcor type coefficients for the higher frequency (800-3000 Hz) band; and, ENERGY data representing higher frequency short term energy level. The three parameters are multiplexed for transmission in binary-code form, thereby representing a recoding of the original binary-coded voice signals.

Process for compressing data relative to voice signals and device

A coding process, given a total number of available bits per unit time, allocates to each of a plurality of signal channels a number of bits proportional to information in the channel. The process is useful for transcoding BCPCM (Block Coded PCM) voice signals for lower bit rate and conserving transmission channel bandwidth.

Quantizing process with dynamic allocation of the available bit

This is a block quantizer which converts a given block of samples into an optimum sequence of numbers describing the sampled signal with minimum distortion due to the quantizing process. The quantizer self-adjusts the basic parameters, i.e., quantizing step Q, d.c. level C and the sequence of numbers fn, describing the signal for each block of samples for a minimal Mean Squared Error.

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Daniel J Esteban