Xilinx, Inc.

Daniel J Downs

Raymond Kong

Richard Yachyang Sun

John J Laurence

Philip Bryn James-Roxby

Sankaranarayanan Srinivasan

Steven A Guccione

Delon Levi

Cameron D Patterson

John D Bunte

Russell J Morgan

Sankaranarayanan Srinivasen

A design hierarchy based on an implementation set abstraction of a user design for an integrated circuit design includes a plurality of nodes and a definition for each of the nodes in the plurality of nodes that describes the type of elements contained in each node and the hierarchy defined by each of the nodes. Each node can include at least one implementation element of the design and the at least one implementation element can be selected among the group including a set of logical elements, a set of placed elements, and a set of placed and routed elements.

Method and arrangement providing for implementation granularity using implementation sets

An integrated circuit operable to wirelessly communicate with other devices by utilizing a radio transceiver and a routing element is disclosed. The routing element is operable to route a signal between various circuit elements and is selectively operable to function as an antenna when coupled with the radio transceiver.

Integrated circuit having a routing element selectively operable to function as an antenna

A method of managing behavior of algorithms includes specifying governing rules/policies that manage I-Set implementation directives, command line options, and environment variables and loading governing rules/policies into a behavior manager. Inside a client tool, the I-Set hierarchy processes and iterates one I-Set node at a time. Without more I-Sets to process, the method is done. If more, then the tool queries the Behavior Manager with an I-Set with symbolic designators of the queried behavior. The Behavior Manager can reply to the client tool indicating whether the queried behavior is to be supported on the appropriate logic of the I-Set node. If the algorithm for the I-Set node lacks the queried behavior, then another I-Set might require processing. If the algorithm for the I-Set node has the queried behavior, then the client tool applies the corresponding algorithm(s) on the appropriate logic.

Method and system for managing behavior of algorithms

A method of designing an integrated circuit using implementation directives for flow control can include the step of loading a design along with specified constraints, creating at least one instance of an data structure formed from a partial netlist, and decomposing at least one set of high level rules into simple implementation directives. The method can further include the steps of selectively attaching the simple implementation directives to the data structure, implementing a task manager which queries a data structure node to create a list of tasks to be performed on the data structure, and executing the list of tasks using a generic flow engine.

Method and system for designing integrated circuits using implementation directives

A method of implementing an integrated circuit design can include the steps of forming a base implementation set and forming a guide implementation set having a plurality of guide implementation set nodes. The method can further include the steps of depositing directives on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of creating and depositing tasks on at least one guide implementation set node (or each node) among the plurality of guide implementation set nodes. The method can further include the steps of invoking each task deposited on guide implementation set nodes as each node in the guide implementation set tree is visited.

Implementation set-based guide engine and method of implementing a circuit design

A method of implementing a user integrated circuit (IC) design in a tree representation includes the step of introducing the tree representation for the user IC design in a partitioned manner including at least one sub-design to form a design abstraction of the user design. At least one sub-design can include a sub-design providing for multiple levels of implementation hierarchy. The method can further include the step of traversing the design abstraction in a top-down fashion to provide functions selected among floor planning, port assignment, and timing budgeting for at least one sub-design, and the step of traversing the design abstraction in a bottom-up fashion to facilitate at least one among resolution of resource conflicts and parallel processing of multiple sub-designs. Traversing the design abstraction in the bottom-up fashion can facilitate a re-budgeting of timing for the integrated circuit design.

Method and system for implementing a circuit design in a tree representation

Method and apparatus for integrating a run-time parameterizable logic core with a static circuit design. A configuration bitstream is generated from a main circuit design that is specified in a hardware description language. The main circuit design includes a first sub-circuit design that specifies a selected subset of resources of the PLD needed by the RTP core and an interface between the RTP core and other parts of the main circuit design. Via execution of a run-time reconfiguration control program, the configuration data that correspond to the first sub-circuit design are replaced with configuration data that implement the RTP core. The run-time reconfiguration program then configures the PLD with the updated configuration bitstream.

Integration of a run-time parameterizable core with a static circuit design

A reconfigurable priority encoding arrangement and method. In various embodiments, the invention identifies, from a plurality of input signals, a highest priority signal that is in a selected state. A priority routing block is implemented on a programmable logic device (PLD). The routing block has a plurality of input ports arranged to receive the respective input signals and a plurality of output ports respectively coupled to the input ports. A priority encoder is also implemented on the PLD and has input ports respectively coupled to the output ports of the priority routing block. Each input port has a priority relative to others of the input ports. The priority encoder is configured to generate an address signal that identifies the input signal having a highest priority and that is in the selected state.

Reconfigurable priority encoding

Described are systems and methods that take advantage of the run-time reconfigurability of modern programmable logic devices to efficiently implement content-addressable memory (CAM) circuits. Rather than using configurable logic to compare CAM entries stored in flip-flops, a CAM in accordance with the invention uses configurable logic for both data storage and comparison. A CAM in accordance with one embodiment of the invention includes a number of programmable look-up tables on a programmable logic device collectively configured to produce a &ldquo;match&rdquo; signal in response to data provided on a series of data input terminals. Configuration data determines the particular pattern to which the CAM responds, so new CAM entries are introduced by configuring (or reconfiguring) one or more of the look-up tables. A processor connected to the PLD responds to new CAM entries by executing instructions that first translate the new CAM entries into configuration data and then employ the configuration data to reprogram the PLD.

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Longmont, CO, United States of America

Daniel J Downs