Agere Systems Inc.

Lsi Corporation

Agere Systems Guardian Corp.

Daniel J Dolan, Jr

Daniel Charles Kerr

Ross Wilson

David W Kelly

Alan Sangone Chen

Zachary A Keirn

Jeffrey A Gleason

Hao Fang

German S Feyh

Michael Straub

Stephen Carl Kuehne

James Patrick Howley

Jun Oie

Charles P Jents

Scott K Glenna

Thomas C Van Eaton

A read/write head for reducing flying height in a disk drive apparatus includes a write transducer for storing data on a storage medium, a read transducer for reading data from the storage medium, and read and write heater elements configured so that during read/write operations, heat dissipated in the read heater element is greater than heat dissipated in the write heater element. A control pad in the head receives current supplied to the read and write heater elements during read and write operations. During the write operation, protrusion of the read/write head attributable to the write transducer and the write heater element is greater than a protrusion of the head attributable to the read heater element. During the read operation, protrusion of the read/write head attributable to the read heater element and the read transducer is greater than a protrusion of the head attributable to the write heater element.

Dual flying height control in a disk drive

An apparatus and method for determining a head parameter value (e.g., head resistance) of a resistive head. A test head current is supplied to the head during a head parameter measurement interval using the same current sources that supply a bias current to the head during an operating (read operation) interval. The determined head parameter value is latched for use in setting the control loop gain for a control loop that controls the current sources during the operating interval.

Method and apparatus for measuring resistance of a resistive sensor

An integrated circuit having an n-channel MOSFET device and a JFET device. The integrated circuit includes a semiconductor layer having an upper surface, an MOS transistor device formed in a doped well of a first conductivity type extending from the semiconductor upper surface and a JFET device. The JFET device includes a channel region in the semiconductor layer spaced from, and having a peak concentration positioned a predetermined distance below, the upper surface. An associated method of manufacturing includes introducing p-type dopant into the semiconductor surface to form a p-well in which the NMOS device is formed and a source and a drain of the JFET device. N-type dopant is introduced into the semiconductor surface to form an n-type region of the NMOS device below the p-well and a gate region of the JFET device. P-type dopant is introduced into the semiconductor layer to simultaneously form a higher concentration p-type region in the p-well of the NMOS device and a channel region extending between the source and drain of the JFET.

Integrated circuit with depletion mode JFET

User data is read from a medium having servo data and user data encoded thereon. The user data is read with a read/write head that is operable in a write mode and a read mode. Servo data is read in a time window following a transition from write mode to read mode, with a frequency passband that has a first low frequency corner. User data is read from the medium after expiration of the time window, with a frequency passband that has a second low frequency corner that is lower than the first low frequency corner.

Reduced recovery time for perpendicular recording systems

A preamplifier chip for a disk drive is modular in layout. Twelve head cells for the preamplifier chip are not lined along the periphery of the chip, but rather are disposed in an array including four rows of three head cells each. The rows are all directed perpendicular to the side with control connection pads. The preferred embodiment allows for a smaller preamplifier chip through increasing the density of head cells on the chip relative to the periphery of the chip usable for head cell connection. The array spaces write portions of the head cells in four spaced lines, minimizing problems associated with heat build up. Spacing between rows of the array can be determined to take maximum advantage of lead pitch on the flex circuit. Modification of the design to a chip for eight or four channels is possible with minimal changes to the design, and minimal reworking of the common circuitry.

Modular preamplifier head circuit layout

Growing community of inventors

Cottage Grove, MN, United States of America

Daniel J Dolan, Jr