Intel Corporation

Daniel J Deleganes

Jonathan P Douglas

James Hadley

Sapumal Wijeratne

Robert D Creek

A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical function on the multiple inputs. A contention interrupt circuit is coupled to one of the pull up and the pull down networks to open circuit the one of the pull up and pull down networks when the pull up and pull down networks are in contention.

Ratioed logic circuits with contention interrupt

A pipelined instruction decoder for a multithread processor including an instruction decode pipeline, a valid bit pipeline, and a thread identification pipeline in parallel together, with each having the same predetermined number of pipe stages. The instruction decode pipeline to decode instructions associated with a plurality of instruction threads. The valid bit pipeline to associate a valid indicator at each pipe stage with each instruction being decoded in the instruction decode pipeline. The thread identification pipeline to associate a thread-identification at each pipestage with each instruction being decoded in the instruction decode pipeline. The pipelined instruction decoder may further include a pipeline controller to control the clocking of each pipe stage of the instruction decode pipeline, the valid bit pipeline, and the thread identification pipeline. The pipeline controller may invalidate an entire thread of instructions, squeeze out invalid instructions, and/or conserve power by selectively stopping the clocking of pipestages.

Pipelined instruction decoder for multi-threaded processors

A multithread pipelined instruction decoder to clock, clear and stall an instruction decode pipeline of a multi-threaded machine to maximize performance and minimize power. A shadow pipeline shadows the instruction decode pipeline maintaining a the thread-identification and instruction-valid bits for each pipestage of the instruction decoder. The thread-id and valid bits are used to control the clear, clock, and stall of each pipestage of the instruction decoder. Instructions of one thread can be cleared without impacting instructions of another thread in the decode pipeline. In some cases, instructions of one thread can be stalled without impacting instructions of another thread in the decode pipeline. In the present invention, pipestages are clocked only when a valid instruction needs to advance in order to conserve power and to minimize stalling.

Method and apparatus for multi-thread pipelined instruction decoder

A precharge circuit for adjusting and maintaining a bitline of a ROM to a pre-determined precharge voltage. The circuit is comprised of P-channel pull-up transistors for initially placing an input line and a node of the precharge circuit at the supply voltage. A relatively small transistor is coupled to the node. Its function is to pull the node's voltage down when a control signal is activated. A larger transistor is also coupled to the node. The larger transistor is used to compensate for the pull down action of the small transistor. The relative sizes of the small transistor versus the larger transistor is made such that the node is placed at the desired quiescent level. The node is maintained at this level until the wordline is activated and the programmed bitline begins discharging. When discharging of the bitline causes the node's voltage to fall below a given threshold voltage through the source follower action of the large transistor, the output from the circuit is pulled down hard to a ground level.

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Hillsboro, OR, United States of America

Daniel J Deleganes