International Business Machines Corporation

Lenovo (Singapore) Pte. Ltd.

Lenovo Enterprise Solutions (Singapore) Pte. Ltd.

Daniel J Colglazier

Marcus Lathan Kornegay

Ngan Ngoc Pham

Cristian G Rojas

Thomas Basilio Genduso

Chris Dombrowski

An apparatus for using a dataless cache entry includes a cache memory and a cache controller configured to identify a first cache entry in cache memory as a potential cache entry to be replaced according to a cache replacement algorithm, compare a data value of the first cache entry to a predefined value, and write a memory address tag and state bits of the first cache entry to a dataless cache entry in response to the data value of the first cache entry matching the predefined value, wherein the dataless cache entry in the cache memory stores a memory address tag and state bits associated with the memory address, wherein the dataless cache entry represents the predefined value, and wherein the dataless cache entry occupies fewer bits than the first cache entry.

Dataless cache entry

A method of managing a direct-mapped cache is provided. The method includes a direct-mapped cache receiving memory references indexed to a particular cache line, using a first cache line replacement algorithm to select a main memory block as a candidate for storage in the cache line in response to each memory reference, and using a second cache line replacement algorithm to select a main memory block as a candidate for storage in the cache line in response to each memory reference. The method further includes identifying, over a plurality of most recently received memory references, which one of the algorithms has selected a main memory block that matches a next memory reference a greater number of times, and storing a block of main memory in the cache line, wherein the block of main memory stored in the cache line is the main memory block selected by the identified algorithm.

Adaptive method for selecting a cache line replacement algorithm in a direct-mapped cache

Apparatuses, systems, methods, and program products are disclosed for cache replacement. An apparatus includes a cache memory structure, a processor, and memory that stores code executable by the processor. The code is executable by the processor to receive a value to be stored in the cache memory structure, identify, in response to determining that the received value is not currently stored in an entry of the cache memory structure, a least recently used ('LRU') set of entries of the cache memory structure where the received value can be stored, and select a least frequently used ('LFU') entry of the identified LRU set of entries for storing the received value.

Less recently and frequently used (LRAFU) cache replacement policy

A method includes storing a first block of main memory in a cache line of a direct-mapped cache, storing a first tag in a current tag field of the cache line, wherein the first tag identifies a first memory address for the first block of main memory, and storing a second tag in a previous miss tag field of the cache line in response to receiving a memory reference having a tag that does not match the tag stored in the current tag field. The second tag identifies a second memory address for a second block of main memory, and the first and second blocks are both mapped to the cache line. The method may further include storing a binary value in a last reference bit field to indicate whether the most recently received memory reference was directed to the current tag field or previous miss tag field.

Alternative direct-mapped cache and cache replacement method

A method, system, and computer program product for providing lines of data from shared resources to caching agents are provided. The method, system, and computer program product provide for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.

Dynamic initial cache line coherency state assignment in multi-processor systems

An improved sectored cache replacement algorithm is implemented via a method and computer program product. The method and computer program product select a cache sector among a plurality of cache sectors for replacement in a computer system. The method may comprise selecting a cache sector to be replaced that is not the most recently used and that has the least amount of modified data. In the case in which there is a tie among cache sectors, the sector to be replaced may be the sector among such cache sectors with the least amount of valid data. In the case in which there is still a tie among cache sectors, the sector to be replaced may be randomly selected among such cache sectors. Unlike conventional sectored cache replacement algorithms, the improved algorithm implemented by the method and computer program product accounts for both hit rate and bus utilization.

Sectored cache replacement algorithm for reducing memory writebacks

A design structure embodied in a machine readable storage medium for designing, manufacturing, and testing a system for providing lines of data from shared resources to caching agents are provided. The system provides for receiving a request from a caching agent for a line of data stored in a shared resource, assigning one of a plurality of coherency states as an initial coherency state for the line of data, each of the plurality of coherency states being assignable as the initial coherency state for the line of data, and providing the line of data to the caching agent in the initial coherency state assigned to the line of data.

Structure for dynamic initial cache line coherency state assignment in multi-processor systems

A cache for use in a memory controller, which processes data in a computer system having at least one processor, and a method for processing data utilizing a cache, are disclosed. The cache comprises a first array such as a tag array, a second array such as a data array, and a pointer for pointing to a portion of the second array that is associated with a portion of the first array, wherein the portion of the second array comprises the data to be processed, and wherein the number of times the at least one processor must undergo a first transfer latency is reduced. This is done by incorporating a prefetch mechanism within the cache. The computer system may include a plurality of processors with each data entry in the data array having an owner bit for each processor. The memory controller may also include a line preloader for prefetching data into the cache. Also, this design can be used in both single processor and multiprocessor systems.

Cache for processing data in a memory controller and a method of use thereof to reduce first transfer latency

A method and system are disclosed for the determination of performance characteristics of a cache design by simulating cache operations utilizing a cache output trace. A first plurality of references are input into a cache during a specified period. In response to the inputs, the cache generates an output which includes a second plurality of references. The output is stored as a trace. The trace may be modified by specifying at least one of the second plurality of references as a particular type of reference. A quantity of the first plurality of references input into the cache during the specified period is determined. Cache operation is simulated utilizing the trace by inputting the trace into a cache simulator. A result of the simulation is determined. Performance characteristics of the cache design are determined utilizing the result of the simulation and the quantity of the first plurality of references.

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Cary, NC, United States of America

Daniel J Colglazier