International Business Machines Corporation

Daniel J Buerkle

Chuck Hong Ngai

Bryan J Lloyd

David Allen Hrusecky

Agnes Yee Ngai

Charles Francis Marino

Ronald S Svec

John William Urda

Ngai, Agnes Y

An apparatus, circuit arrangement, program product and method of scaling an image horizontally partition a source image into a plurality of partitions, with each partition having a width that is no greater than the width of a line buffer used to scale the image. By partitioning an image into a plurality of partitions, the overall width of the scaled image is not constrained by the width of the line buffer. As a result, in many instances line buffers that are significantly smaller than conventional full-width line buffers may be used to generate scaled images that are substantially wider than may be generated by conventional buffers. Moreover, when implemented in hardware, the line buffers typically occupy significantly less real estate on an integrated circuit, thus reducing both cost and power consumption.

Image scaling employing horizontal partitioning

A method and system of operating a digital data decoder. In accordance with this method, a first stream of encoded data is transmitted to the decoder, and a second stream of encoded data is stored in a memory device. One of the first and second streams of encoded data is selected, and the decoder is used to decode that selected stream of encoded data. This second stream of data could have been placed in the memory device by other devices or processes present in an STB system. In this case, all the decoder needs to process the data is a pointer to it and some additional information about, for example, its size. Since the processor has access to all memory, it can do any necessary parsing/manipulation required by the stream format. This provides a large degree of flexibility in this area. The processor can then pass location and attributes of data to the decoder. This also minimizes data movement to/from memory, reducing bandwidth requirements.

Method to play audio and video clips through MPEG decoders

A compression/decompression engine is disclosed for reducing memory requirements of a decode system by storing decoded video data in compressed form. The compression engine comprises parsing chrominance UV data into separate chrominance U data and chrominance V data, and transform logic implementing a Hadamard transformation of multiple bytes of decoded video data in parallel into frequency domain signals. Compression logic is coupled to the transform logic and performs, preferably, a 2:1 transformation of the frequency domain signals to produce compressed video signals for storage in memory. The transform logic and compression logic transform and compress multiple bytes of decoded video data in parallel within a single clock cycle of the decode system. Upon retrieval from memory, the compressed data is returned to original format by the decompression engine, which employs the same transform logic as used by the compression engine. Reassembly logic then returns the separate chrominance U data and chrominance V data to chrominance UV data for use by the associated motion compensation unit or for display.

Compression/decompression engine for enhanced memory storage in MPEG

A mechanism translates a particular macroinstruction into its associated microprogram routine in a general purpose microprogrammed computer. The macroinstruction is capable of execution by either hardware or by microprogram. A table-look up approach is employed for a microprogrammed macroinstruction. The table is embedded in random-access-memory and contains entries representing the origins of various microprogram routines to execute the macroinstruction. The table entries are addressed by bits generated from the operation-code of the macroinstruction. The output of the table is used to address a single level control store containing the microprogram routines. Hardware is assembled in a single facility that is accessible by the microprogram routines to minimize the size of the microprogram routines required to execute the macroinstruction.

System for executing microinstruction routines by using hardware to

A sequence of instructions made up of stages is executed sequentially by the processor in a first mode (stack mode) such that, the Nth stage of the Ith instruction is processed simultaneously with the N+1 stage of the I-1 instruction. Similarly the N+1 stage of the I-1 instruction is processed at the sasme time as the N+2 stage of the I-2 instruction and so on. The processing unit maintains the execution of instructions in the same sequence as they were received by the processing unit by executing all sections of an instruction. Even though a stage may not be required for execution of a particular instruction, the processor must wait (i.e., execute a null instruction) for a time equivalent to a stage before processisng the next stage. The invention provides a second mode (non-stack mode) of execution such that unneeded or null instruction stages are bypassed without the processing order of the execution sequence being disturbed. Sequence logic determines the conditions necessary for a sequence of instructions to be executed in one or the other modes of execution. The processor switches back and forth between stack mode and non-stack mode of processing in order to keep the instructions executing in the same order as they are received by the processor. The non-stack mode of execution allows the processor to utilize wasted time and improve the performance of the processor while the stack mode avoids the need for complex and expensive logic to keep track of out of order instruction processing.

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Newark Valley, NY, United States of America

Daniel J Buerkle