Cypress Semiconductor Corporation

Daniel J Arnzen

Chan-Lon Yang

Usha Raghuram

James E Nulty

Kimberley A Kaufman

James Montague Cleeves

Hanna Bamnolker

Andrey V Zagrebelny

Thurman John Rodgers

Roger F Caldwell

Yitzhak Gilboa

Benjamin C E Schwarz

Ahmad Chatila

Kuantai Yeh

Chan Lon Yan

A non-planar frame base for an image sensor.

Non-planar packaging of image sensor

A method is provided which includes etching one or more layers in an etch chamber while introducing a noble gas heavier than helium into the etch chamber. In a preferred embodiment, the introduction of such a noble gas may reduce the formation of defects within an etched portion of the semiconductor topography. Such defects may include bilayer mounds of nitride and a material comprising silicon, for example. In some embodiments, the method may include etching a stack of layers within a single etch chamber. The stack of layers may include, for example, a nitride layer interposed between an anti-reflective layer and an underlying layer. In addition, the single etch chamber may be a plasma etch chamber designed to etch materials comprising silicon. As such, the method may include etching an anti-reflective layer in a plasma etch chamber designed to etch materials comprising silicon.

Reducing defect formation within an etched semiconductor topography

A dummy structure pattern for fabricating a substantially planar surface within an inactive region of a semiconductor topography is provided. In particular, a semiconductor topography is provided which includes an inactive region comprising a sacrificial annular dummy structure configured to surround an area larger than a square of a minimum critical dimension of a device arranged within an active region of the semiconductor topography. In a preferred embodiment, the area is exclusively designated for a formation of an isolation structure within the semiconductor substrate of the semiconductor topography. As such, a semiconductor topography is provided which includes a separate isolation structure arranged within a spacing of a contiguous isolation structure, which is arranged in a grid pattern within a portion of a semiconductor substrate. Moreover, a semiconductor device is provided which includes an inactive region with a plurality of similarly sized and uniformly arranged annular diffusion regions.

Semiconductor topography having an inactive region formed from a dummy structure pattern

The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus in which a concentration of oxygen at flash striking is greater than a concentration during etching.

Plasma etching method

The present invention relates to a method of plasma etching and a method of operating a plasma etching apparatus.

The present invention relates to semiconductor device containing a via and a method of forming a via in a semiconductor device.

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Eden Praire, MN, United States of America

Daniel J Arnzen