Altera Corporation

Oak Technology, Inc.

Other

Magiclux, LLC

Timelab Corporation

Daniel J Allen

Adam L Carley

James Edward Mandry

Vladimir Levantovsky

Anthony D D'Amelio

Hiroyuki Sakamoto

Randy M Bonella

Thomas J Holman

George E Allen, Jr

Chung W Lam

Vladmir Levantovsky

Leonard R Weisberg

The present invention is a modular exercise system made up of two handles, a segmented track, and two or more sliding carriages. The invention allows a user to safely and incrementally practice front and side split exercises by providing specific and adjustable stability and support. The invention can be extended to accommodate taller users and can also be fully disassembled and packed into a compact travelling configuration.

Modular exercise system

A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms.

Power management of components having clock processing circuits

A system for remote control of lights and small appliances utilizing miniature remote control units, and a method for easily and simply setting which remote controls control which item(s). Unlike conventional remote controls which are moved from place to place, these miniature remote controls are so small they may be removably mounted at each location needed, unobtrusively or even hidden. Receivers for the remote signal are described manufactured within a lamp socket assembly, a very short light bulb socket adapter, the light bulb itself, a wallswitch dimmer and an outlet adapter. One remote control can control multiple receivers, or vice versa, or any other combination, without conflict and with the combination set up or changed more intuitively than in completing systems. Appliances may be turned on or off and lights may be dimmed precisely or set flashing in unison to summon help.

System for light and appliance remote control

A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal.

A shortened adapter for a light bulb socket with highly overlapped male and female parts with an insulating hand-ring that extends only partially over the external surface of the adapter's female threading so it fits into the unthreaded collar of a light bulb socket, thereby significantly reducing the light bulb displacement. The shortened adapter can respond to an incoming signal and control the output of a light bulb. A reversible ring on the insulating hand-ring can change the adapter from being a dimmer to being an on-off control. A mechanism is disclosed to reversibly lock the adapter onto a light bulb. A miniature remote controller to work with the adapter is provided that has many advantages because of its very small size and compact shape. Further, one such controller can control several lights and several such controllers can control a single light in arbitrary combinations selected by the user.

Shortened adapter for light bulb sockets with miniature remote controller

A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a clock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit. In another form, the operation conditions of the VRM or power supply unit are monitored in real-time as a frequency transition is occurring. In addition, control signals to a VRM or power supply may be monitored to control how changes are made to the frequency of a clock signal. Further still, the power available from a VRM or power supply is monitored and a clock signal frequency to one or more system components is controlled to balance the load to the power available from the VRM or power supply.

One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.

Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells

A system and method for generating a clock signal having spread spectrum modulation. The method involves generating a clock signal by generating edge positions for edges of the clock signal from a digital representation of a timing for each edge to impart spread spectrum modulation to the clock signal. A programmable modulator is provided that generates digital values representing edge positions for edges of a clock signal based on at least one of a time-varying period value and a time-varying duty-cycle value. The programmable modulator may comprise a first circuit, called a period modulation circuit, that generates a time-varying digital period value, and a second circuit, called a duty-cycle modulation circuit, that generates a time-varying digital duty-cycle value. The time-varying period values and time-varying duty cycle values are processed to produce a digital edge position value that specifies an edge position for a clock signal. The programmable modulator is coupled to an arbitrary waveform synthesizer that generates timing for edges of the clock signal based on the edge position values. A variety of modulations can be imposed on the clock signal using these techniques, including triangle wave modulation, near-triangle modulation, random and pseudo-random modulation.

Spread spectrum clock signal generation system and method

A waveform generator includes a plurality of delay elements such as in a delay line circuit of a free-running oscillator, phase locked loop (PLL) circuit or delay locked loop (DLL) circuit, an algebra module, a switching module and an output module. The oscillator includes a plurality of delay elements and a plurality of taps disposed between the delay elements, with each tap providing a uniquely phased, oscillating transition signal. The algebra module includes an algebra data input port, a clock input port and an algebra data output port. The algebra module generates a signal at the algebra data output port indicating a first rising edge of the arbitrary waveform in response to a signal received at the algebra data input port. The switching module includes a switch input port in electrical communication with the algebra data output port, a plurality of switch tap input ports in electrical communication oscillator taps and switch output port. At the switch output port, the switch module provides a first transition signal selected from one of the plurality of oscillator taps in response to the signal indicative of a first rising edge received at the switch input port. The output module includes a transition signal input port in electrical communication with the switch output port, a window input port in electrical communication with the algebra data output port and a waveform output port in electrical communication with the clock input port of the algebra module. In order to generate multiple output waveforms, there may be a plurality of switching modules and a corresponding plurality of output modules. Each corresponding switching module/output module pair is dedicated to producing a corresponding output signal.

Arbitrary waveform synthesizer to generate one or more arbitrary waveforms

A method and circuit for processing a serial data stream carrying data at a rate established by an underlying clock signal, the method and circuit involving: time-stamping each of the transitions of a sequence of transitions within the serial data stream to thereby generate a sequence of time stamps; and based at least in part on the sequence of time-stamps, recovering the data from the serial data stream.

Clock and data recovery method and apparatus

A method and system for managing power consumption of a component that employs a clock processing circuit to produce a processed clock signal used by the component from a clock signal supplied to the clock processing circuit. A frequency of a clock signal supplied to the clock processing circuit is changed based on operating characteristics of a voltage regulator module (VRM) or power supply unit so as to maintain acceptable operating parameters of the power supply unit during a change in frequency of a cock signal. Data pertaining to operating characteristics of the VRM or power supply may be one or both of two forms. In one form, this data is determined a priori from simulations or experiments made on a particular VRM or power supply unit and used to generate and store parameters that are known to optimally (quickly and without degradation of VRM or power supply performance) change the frequency of the clock processing circuit. In another form, the operation conditions of the VRM or power supply unit are monitored in real-time as a frequency transition is occurring. In addition, control signals to a VRM or power supply may be monitored to control how changes are made to the frequency of a clock signal. Further still, the power available from a VRM or power supply is monitored and a clock signal frequency to one or more system components is controlled to balance the load to the power available from the VRM or power supply.

A digitally programmable delay circuit comprising a plurality of transistors connected in parallel with each other and to a line carrying a signal having an edge to be delayed. One or more of the transistors are selected by a delay control signal to impose a delay amount to the edge, wherein the delay control signal is based on a desired delay amount and a measure of instantaneous process, voltage and temperature conditions of an integrated circuit in which the plurality of transistors are implemented. A selector circuit is responsive to the delay control signal and converts the delay control signal into one or more transistor selection signals to activate one or more of the plurality of transistors. The plurality of transistors may comprise a first sub-circuit having a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other in a ladder configuration, and a second sub-circuit comprising a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other and in a ladder configuration. The overall delay imposed on the edge after it has passed through both sub-circuits has delay contributions from both types of transistors. The delay circuit may have enhanced performance because of finer delay control granularity by providing a first circuit stage that comprises a plurality of transistors for relatively fine delay adjustment to the edge and a second circuit stage that comprises a plurality of transistors for relatively coarse delay adjustment to the edge. A combination of one or more of the transistors in the first and second circuit stages may be selected to produce numerous steps or increments of delay adjustability.

Digitally programmable delay circuit with process point tracking

A clock signal generation system and method to distribute at least one clock signal to a plurality of points on a circuit board using a plurality of digitally programmable delay circuits each of which delays the clock signal by a desired amount so as to synchronize arrival of the clock signal when distributed to each of the plurality of points on the circuit. Each digitally programmable delay circuit comprises a plurality of circuit stages connected in series with each other. Each circuit stage comprises a plurality of transistors of a first type (e.g., P-type) connected in parallel with each other, and a plurality of transistors of a second type (e.g., N-type) connected in parallel with each other. In each circuit stage, one or more of the plurality of transistors of the first type are selected to delay a rising edge, and one or more of the plurality of transistors of a second type are selected to delay a falling edge.

Delay circuit for synchronizing arrival of a clock signal at different circuit board points

An ice fishing trap comprising a main body supporting a rotatable spool for supporting a desired length of fishing line. An indicator, having both a set position and a triggered position, is supported by the main body. A release rod cooperates with the rotatable spool and, when the indicator is in its set position, and also cooperates with the indicator. The release rod has a first position in which the release rod captively retains the indicator in its set position and engages with the spool and the release rod has a second position, axially spaced from the first position, in which the release rod releases the indicator to permit the indicator to move to its triggered position, and rotation of the spool moves the release rod from its first position to its second position to actuate the indicator into its triggered position.

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Derry, NH, United States of America

Daniel J Allen