Advanced Micro Devices Corporation

Daniel Hopper

David A Kaplan

Benjamin Charles Serebrin

John M King

Tarun Nakra

Christopher D Bryant

Jeff Rupley

Suzanne Plummer

Embodiments herein provide for improved store-to-load-forwarding (STLF) logic and linear aliasing effect reduction logic. In one embodiment, a load instruction to be executed is selected. Whether a first linear address associated with said load instruction matches a linear address of a store instruction of a plurality of store instructions in a queue is determined. Data associated with said store instruction for executing said load instruction is forwarded, in response to determining that the first linear address matches the linear address of the store instruction.

Unified store queue for reducing linear aliasing effects

The present invention provides a method and apparatus for allocating store queue entries to store instructions for early store-to-load forwarding. Some embodiments of the method include allocating an entry in a store queue to a store instruction in response to the store instruction being dispatched and prior to receiving a translation of a virtual address to a physical address associated with the store instruction. The entry includes storage for data to be written to the physical address by the store instruction.

Allocating store queue entries to store instructions for early store-to-load forwarding

A method and apparatus for branch determination is disclosed. The method includes a first command issuing within a computer processor. Execution of the first command by the computer processor includes evaluating one or more conditions to set one or more flags. Subsequent to the first command issuing, a second command is issued and executed. Execution of the second command includes causing the computer processor to wait until the one or more flags are set. Subsequent to the first and second commands issuing, a third command is issued and executed. Execution of the third command includes performing a jump operation based on a value of at least one of the one or more flags set by the first command.

Early branch determination

A method and apparatus are provided to control the order of execution of load and store operations. Also provided is a computer readable storage device encoded with data for adapting a manufacturing facility to create the apparatus. One embodiment of the method includes determining whether a first group, comprising at least one or more instructions, is to be selected from a scheduling queue of a processor for execution using either a first execution mode or a second execution mode. The method also includes, responsive to determining that the first group is to be selected for execution using the second execution mode, preventing selection of the first group until a second group, comprising at least one or more instructions, that entered the scheduling queue prior to the first group is selected for execution.

Scheduling scheme for load/store operations

A method and mechanism for managing shifts in a shifting queue. A reservation station in a processing device includes a queue of shifting entries. On a given cycle, zero, one, or two instructions may be dispatched and stored in the queue. Depending upon the dispatch conditions and the state of the queue, existing entries within the queue may be shifted to make room for the newly dispatched instruction(s) at the top of the queue. Shift vectors are generated which identify entries of the queue which are to be shifted and by how much. A queue management approach is adopted in which three rules are generally followed: (i) Only shift entries that must shift due to dispatch pressure from above; (ii) If an entry must be shifted elsewhere, shift it as far down the array as the particular implementation allows; and (iii) Don't allow the previous conditions to force additional entries to shift that are not required to shift by dispatch pressure.

Growing community of inventors

Austin, TX, United States of America

Daniel Hopper