International Business Machines Corporation

S3 Graphics Co., Ltd.

Daniel H McCabe

Gerald George Pechanek

Leon Lumelsky

Larry D Larsen

Bruce D Lucas

Steven P Larky

Alan W Peevers

Peter Alexander Manson

Clair John Glossner

Stamatis Vassiliaadis

Todd K Rodgers

A parallel architecture for determining pixels inside a graphics primitive is provided. The architecture is a pipeline structure having a predetermined number of sequential logic circuits connected in series followed by a predetermined number of parallel logic circuits arranged in a pyramid structure. Each sequential logic circuit uses arithmetic edge functions corresponding to edges of a graphics primitive to determine whether a polygonal portion of a raster image is inside the graphics primitive. If the polygonal portion is at least partly inside the graphics primitive, the sequential logic circuit divides the polygonal portion into a predetermined number of subportions and computes descriptors (e.g., vertices and translated edge functions) for each subportion sequentially. Descriptors are then transferred sequentially to the next stage. Each parallel logic circuit performs the same functions as that of a sequential logic circuit except that a parallel logic circuit computes descriptors of the subportions in parallel and transfers them to the next stage in parallel.

Parallel architecture for graphics primitive decomposition

A processing system is disclosed. The processing system processes a plurality of commands for a peripheral system. A command source generates at least a first command stream and a second command stream. A portion of the peripheral system is responsive to the second command stream and the entire processing system is responsive to the first command stream. The processing system includes a command segregation module that receives the plurality of commands from the command source. The command segregation module also segregates each command into the first command stream and the second command stream and inserts synchronization commands into the first command stream. The processing system also includes a command integration module that receives the first command stream and the second command stream. The command integration module integrates the first command stream having the synchronization commands and the second command stream so that there is a single, linearized command stream. One or more execution modules of the processing system may now execute the linearized command stream. A method for processing a plurality of command streams is also disclosed.

Command interpretation system and method

A method for frequency modulation synthesis and apparatus for performing the method. The method uses additions rather than multiplies and therefore saves the space and cost of multipliers in circuit implementations. The method saves further resources by using the coordinate rotation digital computer (CORDIC) algorithm to acquire sine values as opposed to an extensive sine look-up table. The method can be implemented with either a dedicated digital circuit or a programmed special purpose processor such as a digital signal processor. The hardware for implementing the method is normally integrated onto a semiconductor device.

Method and apparatus for frequency modulation synthesis

An array processor topology reconfiguration system and method enables processor elements in an array to dynamically reconfigure their mutual interconnection for the exchange of arithmetic results between the processors. Each processor element includes an interconnection switch which is controlled by an instruction decoder in the processor. Instructions are broadcast to all of the processors in the array. The instructions are uniquely interpreted at each respective processor in the array, depending upon the processor identity. The interpretation of the commonly broadcast instruction is uniquely performed at each processor by combining the processor identity for the executing processor, with a value in the instruction. The resulting control signals from the instruction decoder to the interconnection switch, provides for a customized linkage between the executing processor and other processors in the array.

Selective processing and routing of results among processors controlled

A circuit for interfacing between a digital-television circuit for producing pixel data for television images and a computer graphics display permits rapid scaling and positioning of live television images on the graphics display. In a preferred embodiment, the digital-television/computer-graphics interface circuit of the invention includes memory for storing a horizontal-scaling bit pattern and a vertical-scaling bit pattern. Such a preferred interface circuit is adapted to receive digital-television pixel data from the digital television circuit and, on a pixel-by-pixel basis depending on the state of corresponding bits in the horizontal-scaling bit pattern, to skip the pixel in the case of image contraction and to replicate the pixel in the case of image expansion. The preferred interface circuit is also adapted to receive digital-television pixel data on a television-line by television-line basis and, depending on the state of a corresponding bit of the vertical-scaling bit pattern, to skip the entire line of pixel data in the case of image contraction or to replicate the line in the case of image expansion. The interface circuit may include a hardware vector generator for generating scaling bit patterns in accordance with a procedure analogous to a vector-drawing procedure used in graphics displays, such as the 'Bresenham procedure.'

Color television window for a video display unit

A color display device which includes dither apparatus for each primary color to be displayed. A dither matrix provides a dither signal output as a function of the position of a pixel on the color display device. An input primary color signal includes an integer signal and a fraction signal. The integer signal is incremented by an incrementer. There is means for providing an output primary color signal which is the incremented signal whenever a predetermined relationship exists between the dither signal and the fraction signal, and which is the integer signal whenever the predetermined relationship does not exist.

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Bellevue, WA, United States of America

Daniel H McCabe