International Business Machines Corporation

Daniel Guy Young

Casimer M DeCusatis

Edward Joseph Seminaro

Steven John Baumgartner

Robert Russell Williams

Timothy Clyde Buchholtz

Aruna V Ramanan

Alison B White

Joseph James Cahill

Anthony Richard Bonaccio

Steven Michael Douskey

Andrew Benson Maki

Thomas W Liang

Paul Allen Ganfield

Jeffrey Douglas Brown

George Wayne Nation

David W Siljenberg

Mark Robert Funk

Andrew Douglas Davies

Charles Porter Geer

Curtis Walter Preuss

Thomas James Osten

Dana Marie Woeste

Paul Gary Reuland

Christopher John Kimble

Scott A Hilker

William A Hammond, Jr

John Steven Mitby

Thomas J Beacom

Vimal Ramannhai Patel

David LeRoy Guertin

Daniel Bravo Lacap

Thomas Pham

A method of validating a configuration of a computer clusters includes transmitting a first neighbor identification to a first flexible service processor (FSP) arranged in the first computer cluster and a second neighbor identification to a second FSP arranged in the second computer cluster, connecting a first end of a cable to a first transceiver arranged in the first cluster and connecting a second end of the cable to a second transceiver arranged in the second cluster. The first neighbor identification is passed from the first transceiver to the second computer cluster and the second neighbor identification is passed from the second transceiver toward the first computer cluster. The first neighbor identification is compared with a desired first neighbor identification to establish a first comparison result, and the second neighbor identification is compared with a desired second neighbor identification to establish a second comparison result and a notice is generated.

Configuration validation system for computer clusters

A method of validating multi-cluster computer interconnects includes calculating a cable interconnect table associated with the multi-cluster computer, and distributing the cable interconnect table to a first transceiver in the first computer cluster and a second transceiver in the second computer cluster. The method also includes connecting a first end of a cable to the first transceiver and a second end of the cable to the second transceiver, transmitting a first neighbor identification from the first cluster to the second cluster, and a second neighbor identification from the second cluster to the first cluster, comparing the first neighbor identification with a desired first neighbor identification from the cable interconnect table to establish a first comparison result and the second neighbor identification with a desired second identification from the cable interconnect table to establish a second comparison result, and generating an alert based on the first and second comparison results.

Validation of computer interconnects

A phase locked loop generates an output corresponding to a source synchronous input and an input link clock signal. A phase locking feedback system receives the input and an input link clock signal and detects phase deviations between the output and the input. The phase locking feedback system also adjusts an adjusted clock signal based on the phase deviations thereby causing the phase locking feedback system to generate the output so that the output has a steady phase relationship with the input. A first mechanism causes the phase locking feedback system not to track phase deviations between the output and the input upon occurrence of a first predefined event, thereby maintaining the adjusted clock signal at a current state.

Unlock mode in source synchronous receivers

Techniques and apparatus for testing phase rotators for detecting defective tap weights are provided. Phase rotator test logic may include a master phase rotator to cycle the phase of a clock signal distributed to operational phase rotators through an entire cycle of phases (e.g., an entire 360 degree rotation). Each operational phase rotator should respond with an equal but opposite phase shift in order to maintain phase lock. Thus, after sweeping, each tap weight is exercised, which may help ensure defective tap weights in any (e.g., quadrant) are detected during testing.

Phase rotator control test scheme

A method and apparatus are provided for implementing power control in multi-voltage input/output (I/O) circuits. First current biasing devices are provided for creating a first constant bias current. Second current biasing devices are provided for creating a second bias current. The second current biasing devices are activated at a first voltage and are deactivated at a second voltage. The first voltage is less than the second voltage.

Method and apparatus for implementing power control in multi-voltage I/O circuits

A high speed voltage level shifter and phase splitter circuit is provided. The voltage level shifter and phase splitter circuit includes an input signal and a first input inverter stage that receives the input signal and provides an inverted delayed out of phase signal to the input signal. A buffer stage receives the input signal and provides a buffered delayed in phase signal to the input signal. A first constant current source is coupled between the first input inverter stage and the buffer stage. A first output inverter stage is coupled to the first constant current source and provides a voltage level shifted and out of phase signal to the input signal. A second constant current source is coupled between the first input inverter stage and the buffer stage having an opposite polarity as the first constant current source. A second output inverter stage is coupled to the second constant current source and providing a voltage level shifted and in phase signal to the input signal.

Voltage level shifter and phase splitter

A mixed voltage output driver includes an output sensing circuit that senses an output voltage at an output terminal and generates a voltage signal that corresponds to a voltage level at the output terminal. Next, an impedance selection circuit receives the voltage signal and generates a control signal in response to the output voltage having a higher logical uplevel than the mixed voltage output driver. The control signal is then received by an adjustable drive impedance circuit that is also coupled to an input terminal of the mixed voltage output driver and, in response thereto, the adjustable drive impedance circuit modifies an output drive impedance of the mixed voltage output driver. In another advantageous embodiment, the mixed voltage output driver only determines if the output voltage at the output terminal is at a logical uplevel before adjusting the output drive impedance.

Mixed voltage output driver with automatic impedance adjustment

A boundary configuration (Common Input/output CIO) for Generalized Scan Designs (GSD) in a single clock chip design includes at least one generalized scan design internal latch; a boundary scan clock input to the internal latch; an input/output cell connected to the internal latch; and at least one control line between the internal latch and the input/output cell. The CIO GSD is arranged and configured to operate in various modes including a function mode, a RUNBIST/INTEST/LBIST mode, an EXTEST/WIRETEST mode, a SAMPLE/PRELOAD mode, etc. In a different version, a MUX controller is connected to the internal latch. The MUX controller selects data from one of at least two control lines and sending the selected data to at least one internal logic unit of the chip for a test operation.

Boundary scan latch configuration for generalized scan designs

A communication system for an array of DASD includes a plurality of loop resiliency circuits and a plurality of selection circuits. The DASD array includes a plurality of DASD slots. Each DASD slot may receive a DASD, and each DASD receives power from a regulator. The loop resiliency circuits form at least a first communication path. Each loop resiliency circuit is associated with one of the DASD slots and selectively includes the associated DASD slot in the first communication path based on a selection signal. The plurality of selection circuits are also associated with one of the DASD slots; and therefore, are also associated with one of the plurality of loop resiliency circuits. Each selection circuit is connected to the associated DASD slot and receives output from the regulator in the associated DASD slot. Based on the regulator output, or a lack thereof, the selection circuit generates a selection signal for the associated loop resiliency circuit. Besides being serially connected to form a single communication path, the loop resiliency circuits can be divided into groups wherein the loop resiliency circuits in each group are serially connected to form a communication path. Separate loop resiliency circuits then selectively connect these communication paths to a main communication path including an initiator. As a further alternative, a second initiator can be selectively placed in one of the communication paths via another loop resiliency circuit.

Communication system for an array of direct access storage devices

The present invention is a driver circuit for interfacing electronic components which have different supply voltages. The driver circuit includes a source terminal for receiving a source voltage, an output terminal connected to an off-chip electronic component, and a pull up circuit disposed between the source and output terminals for providing a field effect controlled current path between the source terminal and the output terminal. The pull up circuit includes a first transistor in series with a second transistor, the second transistor providing overvoltage stress relief for the first transistor.

Voltage upwardly compliant CMOS off-chip driver

The present invention provides a method in a data processing system for efficiently sending a data packet from a source node to a destination node. The data processing system includes a multi-segment network having at least two segments, wherein the source node and the destination node are located within in different segments. Communication of a data packet from one segment to another segment is provided by an agent node. The present invention generates a data packet at the source node within a first segment on the multi-segment network. The data packet includes a source address, a destination address, and data. The data packet is then transmitted within the first segment and the source node retains ownership of the data packet. Thereafter, the data packet is received within the first segment at an agent node. The data packet is examined to determine the destination address and then transmit it to the destination node within a second segment in the multi-segment network. The data packet is thereafter received at the destination node within the second segment and an echo packet is automatically transmitted from the destination node to the source node to indicate a successful reception of the data packet and transferring ownership of the data packet from the source node to the destination node.

System for transferring ownership of transmitted data packet from source

A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.

Growing community of inventors

Rochester, MN, United States of America

Daniel Guy Young