Intel Corporation

Lantiq Deutschland Gmbh

Infineon Technologies Ag

Maxlinear, Inc.

Maxlinear Asia Singapore Pte Ltd

Daniel Gruber

Kameran Azadet

Martin Clara

Ramon Sanchez

Hundo Shin

Michael Kalcher

Christian Lindholm

Giacomo Cascio

Albert Molina

Franz Kuttner

Matteo Camponeschi

Davide Ponton

Yu-Shan Wang

Andreas Wiesbauer

Richard Gaggl

Luis Hernandez

Edwin Thaller

Mark L Elzinga

Francesco Conzatti

Christian Fleischhacker

Patrizia Greco

Dietmar Sträussnigg

Marc Jan Georges Tiebout

Alan Paussa

L Mark Elzinga

Michael Fulde

Matej Kus

Stefan Trampitsch

Klatzer Wolfgang

Stefan Matschitsch

Alessandra Cangianiello

A digital-to-analog converter (DAC). A DAC includes a plurality of DAC cells and a controller. The controller generates a control signal for driving the plurality of DAC cells for each clock cycle. The controller may generate the control signal to select a set of one or more DAC cells for an input code or for a standby mode of the DAC such that the selected set of one or more DAC cells to be active for the same input code or for the standby mode of the DAC change over time without affecting an output of the DAC more than a predetermined limit.

Digital-to-analog converter and a method for reducing aging effects on components of the digital-to-analog converter

A system and method for calibrating a time-interleaved digital-to-analog converter (DAC). A calibration signal generator generates calibration data, and a time-interleaved DAC converts the calibration data to an analog calibration signal. An observation analog-to-digital converter (ADC) samples, and quantizes, the analog calibration signal filtered by an anti-alias filter. A mismatch estimation block estimates a frequency response mismatch between the sub-DACs and generates a sub-DAC mismatch correction factor based on an output of the observation ADC. The calibration signal generator applies the sub-DAC mismatch correction factor to the calibration data. The mismatch estimation block may estimate a DC offset mismatch between the sub-DACs based on the output of the observation ADC and generates a DC offset correction factor, and the calibration signal generator applies the DC offset correction factor to the calibration data.

System and method for calibrating a time-interleaved digital-to-analog converter

A processing device is provided. The processing device comprises one or more interfaces configured to transmit information to a nonlinear device and processing circuitry configured to control the one or more interfaces and to. Further, the processing circuitry is configured to transmit an excitation signal to the nonlinear device and to receive response information from the nonlinear device. Further, the processing circuitry is configured to determine a linear response of the nonlinear device based on the response information and to determine a nonlinear response of the nonlinear device based on the determined linear response.

Processing device, transmitter, base station, mobile device, method and computer program

An apparatus for analog-to-digital conversion is provided. The apparatus includes a first analog-to-digital converter (ADC) configured to receive an input signal and convert the input signal to a sequence of M-bit digital values. The apparatus further includes a second ADC including a plurality of time-interleaved sub-ADCs each being configured to receive the input signal and at least one M-bit digital value of the sequence of M-bit digital values. Further, each of the plurality of time-interleaved sub-ADCs is configured to convert the input signal to a respective sequence of B-bit digital values using the at least one M-bit digital value of the sequence of M-bit digital values. M and B are integers with M<B.

Apparatus for analog-to-digital conversion, systems for analog-to-digital conversion and method for analog-to-digital conversion

Circuitry for digital-to-analog conversion is provided. The circuitry includes a driver circuit and a weighting resistor circuit coupled to an output of the driver circuit. The weighting resistor circuit includes a first resistive sub-circuit coupled to the output of the driver circuit and an intermediate node. The weighting resistor further includes a second resistive sub-circuit coupled to the intermediate node and a common node. Further, the weighting circuit includes a third resistive sub-circuit coupled to the intermediate node and an output of the circuitry. The resistivity of the second resistive sub-circuit is equal to or smaller than the resistivity of the first resistive sub-circuit.

Circuitry for digital-to-analog conversion, differential systems and digital-to-analog converter

A semiconductor device comprising at least one transmit path is provided. The transmit path comprises an input node for receiving a digital baseband signal. Further, the transmit path comprises digital mixer circuitry coupled to the input node and configured to generate an upconverted digital baseband signal by upconverting a frequency of the digital baseband signal. Additionally, the transmit path comprises Digital-to-Analog Converter (DAC) circuitry coupled to the digital mixer circuitry and configured to generate an analog radio frequency signal based on the upconverted digital baseband signal. The transmit path comprises first analog mixer circuitry coupleable to an output of the DAC circuitry, and second analog mixer circuitry coupleable to the output of the DAC circuitry. Further, the transmit path comprises a first output node coupleable to an output of the first analog mixer circuitry, and a second output node coupleable to an output of the second analog mixer circuitry.

Semiconductor devices, transceiver, base station and mobile device

An attenuator circuit is provided. The attenuator circuit includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair. Further, the attenuator circuit includes a first plurality of resistive elements coupled in series between the first input node and a first output node for outputting a first output signal. The attenuator circuit additionally includes a second plurality of resistive elements coupled in series between the second input node and a second output node for outputting a second output signal. In addition, the attenuator circuit includes a shunt path coupled to a first intermediate node and a second intermediate node. The first intermedia node is arranged between two resistive elements of the first plurality of resistive elements. The second intermedia node is arranged between two resistive elements of the second plurality of resistive elements. The shunt path comprises a switch circuit configured to selectively couple the first intermediate node and the second intermediate node based on one or more control signals.

Attenuator circuit, receiver, base station, mobile device and method for operating an attenuator circuit

Examples relate to a buffered flipped voltage follower circuit arrangement, low dropout voltage regulators, a capacitive digital-to-analog converter, a transceiver for wireless communication, a mobile communication device, a base station transceiver, and to a method for forming a buffered flipped voltage follower circuit arrangement. The buffered flipped voltage follower circuit arrangement comprises a first transistor (M) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a second transistor (M) comprising a first terminal, a second terminal and a gate terminal. The buffered flipped voltage follower circuit arrangement comprises a buffer circuit comprising an input terminal and an output terminal. The buffered flipped voltage follower circuit arrangement a feed-forward compensation circuit (−g) comprising an input terminal and an output terminal. The first terminal of the first transistor (M) is coupled to a supply voltage of the flipped voltage follower circuit. The second terminal of the first transistor (M) is coupled with the first terminal of the second transistor (M) and with an output voltage terminal of the buffered flipped voltage follower circuit arrangement. The second terminal of the second transistor (Mc) is coupled with the input terminal of the buffer circuit and with the output terminal of the feed-forward compensation circuit (−g). The gate terminal of the first transistor (MP) is coupled with the output terminal of the buffer circuit and with the input terminal of the feed-forward compensation circuit (−g).

Concept for a buffered flipped voltage follower and for a low dropout voltage regulator

A reference buffer circuit for an analog-to-digital converter is provided. The reference buffer circuit includes a first input node configured to receive a first bias signal of a first polarity from a first signal line. Further, the reference buffer circuit includes a second input node configured to receive a second bias signal of a second polarity from a second signal line. Additionally, the reference buffer circuit includes a first output node configured to output a first reference signal of the first polarity. A first buffer amplifier is coupled between the first input node and the first output node. The reference buffer circuit includes in addition a second output node configured to output a second reference signal of the second polarity. A second buffer amplifier is coupled between the second input node and the second output node. Further, the reference buffer circuit includes a first coupling path comprising a first capacitive element. The first coupling path is coupled between the first output node and the second input node. In addition, the reference buffer circuit includes a second coupling path comprising a second capacitive element. The second coupling path is coupled between the second output node and the first input node.

Reference buffer circuit, analog-to-digital converter system, receiver, base station and mobile device

An apparatus for correcting a mismatch between a first segment and a second segment of a Digital-to-Analog Converter, DAC, is provided. The first segment generates a first contribution to an analog output signal of the DAC based on a first number of bits of a digital input word for the DAC converter, and the second segment generates a second contribution based on a second number of bits. Further, the apparatus comprises a first processing circuit for the first number of bits comprising a first filter configured to modify the first number of bits to generate first modified bits, and a second processing circuit comprising a second filter to modify the second number of bits to generate second modified bits. The apparatus additionally comprises an output configured to output a modified digital input word for the DAC, which is based on the first modified bits and the second modified bits.

Apparatus for correcting a mismatch, digital-to-analog converter system, transmitter, base station, mobile device and method for correcting a mismatch

A Digital-to-Analog Converter (DAC) is provided. The DAC includes a code converter circuit configured to sequentially receive first digital control codes for controlling N digital-to-analog converter cells. N is an integer greater than one. The code converter circuit is further configured to convert the first digital control codes to second digital control codes. Additionally, the DAC includes a bit-shifter circuit configured to receive shift codes for the second digital control codes. The shift codes are obtained using dynamic element matching and indicate a respective circular shift by rbit positions for the i-th second digital control code, wherein ris an integer smaller than N−1. The bit-shifter circuit is further configured to generate third digital control codes by circularly shifting the second digital codes based on the shift codes. In addition, the DAC includes a cell activation circuit configured to selectively activate one or more of the N digital-to-analog converter cells based on the third digital control codes.

Digital-to-analog converter, transmitter, base station, mobile device and method for a digital-to-analog converter

An input buffer circuit for an analog-to-digital converter is provided. The input buffer circuit includes a buffer amplifier. The buffer amplifier includes a first input node and a second input node each configured to receive a respective one of a first input signal and a second input signal forming a differential input signal pair for the analog-to-digital converter. The buffer amplifier further includes a first output node and a second output node each configured to output a respective one of a first buffered signal and a second buffered signal. In addition, the input buffer circuit includes feedback circuitry. The feedback circuitry is configured to generate, based on the first buffered signal and the second buffered signal, a first feedback signal and a second feedback signal for mitigating a respective unwanted signal component at the first input node and the second input node related to a limited reverse isolation of the amplifier buffer. The feedback circuitry is further configured to supply the first feedback signal to the first input node and the second feedback signal to the second input node.

Input buffer circuit, analog-to-digital converter system, receiver, base station, mobile device and method for operating an input buffer circuit

A semiconductor chip providing on-chip self-testing of an Analog-to-Digital Converter, ADC, implemented in the semiconductor chip is provided. The semiconductor chip comprises the ADC and a Digital-to-Analog Converter, DAC, configured to generate and supply a radio frequency test signal to the ADC via a supply path. The ADC is configured to generate digital output data based on the radio frequency test signal. The semiconductor chip further comprises a reference data generation circuit configured to generate digital reference data. Additionally, the semiconductor chip comprises a comparator circuit configured to compare the digital output data to the digital reference in order to determine error data.

Semiconductor chip providing on-chip self-testing of an ana-log-to-digital converter implemented in the semiconductor chip

The present disclosure relates to a concept for a transformer, a transmitter circuit, a semiconductor chip, a semiconductor package, a base station, a mobile device and a method for a radio frequency transmitter. The transformer for a radio frequency transmitter circuit comprises a primary coil and a secondary coils, which are configured to receive an input signal and to provide an output signal, and a ternary coil configured to provide a feedback signal.

Transformer, transmitter circuit, semiconductor chip, semiconductor package, base station, mobile device, and method for a radio frequency transmitter

A Digital-to-Analog Converter, DAC, is provided. The DAC comprises one or more first DAC cells configured to generate a first analog signal based on first digital data. The one or more first DAC cells are coupled to a first output node for coupling to a first load. The DAC comprises one or more second DAC cells configured to generate a second analog signal based on second digital data. The one or more second DAC cells are coupled to a second output node for coupling to a second load. The one or more first DAC cells and the one or more second DAC cells are couplable to a power supply for drawing a supply current. The DAC further comprises a data generation circuit configured to generate the second digital data based on the first digital data.

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St. Andrae, Austria

Daniel Gruber