Intel Corporation

Six Degrees Space Ltd

Cisco Technology, Inc.

Daniel Greenspan

Asaf Rubinstein

Yoav Lossin

Blaise B Fanning

Supratik Majumder

Klonymus Sholom Lieberman

Zvika Greenfield

Anant V Nori

Julius Yuli Mandelblat

Randy B Osborne

Nagi Aboulenein

Israel Diamand

Aviad J Wertheimer

Marc D Torrant

A positioning unit mountable on a moving object includes at least one light source measuring unit and a processor. The light source measuring units have high directional sensitivity along a first axis and low directional sensitivity along a second axis orthogonal to the first axis to capture relative angular information of the moving object with respect to a plurality of simultaneously active stationary light sources located at multiple locations in a space. The processor determines positioning information of the moving object at least from the output of the at least one light source measuring unit. Each light source measuring unit includes an optical arrangement and a linearly configured imaging sensor to receive light from the stationary light sources through the optical arrangement.

Method and apparatus for indoor positioning

A sensing module includes a linear image sensor and an optical unit. The unit includes an optical element having a curved, outward surface and a covering on the outward surface. The covering has a slit formed therein. The optical unit faces the sensor with the slit perpendicular to a longitudinal axis of the sensor and images a wide field of view onto a single pixel of the linear sensor, wherein light impinging normal to the slit, at any location along the slit, is imaged on a central pixel of the sensor while light impinging one of a plurality of non-normal angles to the slit is imaged on an associated one of a plurality of non-central pixels of the sensor.

Wide field of view optical module for linear sensor

A positioning unit mountable on a moving object includes at least one light source measuring unit and a processor. The light source measuring units have high directional sensitivity along a first axis and low directional sensitivity along a second axis orthogonal to the first axis to capture relative angular information of the moving object with respect to a plurality of stationary light sources in a space. The processor determines positioning information of the moving object at least from the output of the at least one light source measuring unit. Each light source measuring unit includes an optical arrangement and a linearly configured imaging sensor to receive light from the stationary light sources through the optical arrangement.

A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy.

Apparatus and method for shared least recently used (LRU) policy between multiple cache levels

Interleaved cache controllers with shared metadata are disclosed and described. A memory system may comprise a plurality of cache controllers and a metadata store interconnected by a metadata store fabric. The metadata store receives information from at least one of the plurality of cache controllers, a portion of which is stored as shared distributed metadata. The metadata store provides shared access of the shared distributed metadata hosted to the plurality of cache controllers.

Interleaved cache controllers with shared metadata and related devices and systems

A cache controller is to allocate memory within set-associative cache that includes a plurality of sets of ways. The cache controller is to request to assign an entry for a system address in the set-associative cache and execute a function to determine a set, from a series of sets within the plurality of sets of ways, to which to allocate the entry in the set-associative cache. The cache controller is further to identify an available number of ways in the set and identify a way that is available in response to execution of a way bias algorithm. The cache controller is also to determine whether the way is among the ways available within the set and select the way for allocation of the entry in response to the way being among the ways available within the set.

Create page locality in cache controller cache allocation

A sensing module includes a high speed, linear image sensor and an optical unit facing the sensor. The unit includes an optical element having a curved surface and a covering on an outward surface of the optical element. The covering has a slit formed therein. The optical unit images a wide field of view onto a single pixel of the linear sensor, wherein light impinging normal to the slit, at any location along the slit, is imaged on a central pixel of the linear sensor while light impinging at a non-normal angle to the slit, at any location along the slit, is imaged on a non-central pixel of the linear sensor.

In an embodiment, a processor includes at least one core and a first cache memory including a first plurality of sets having a first plurality of cache lines and associated metadata to store address information, recency information and a first indicator to indicate whether the cache line is associated with an oversubscribed set of a second cache memory. A first cache controller may be configured to base an eviction decision with regard to a first set of the first plurality of sets including a first cache line at least in part on the first indicator of the first cache line. Other embodiments are described and claimed.

Multi-level cache with associativity collision compensation

A method of transition minimized low speed data transfer is described herein. In an embodiment, a data rate of a set data to be transmitted on a data bus is determined. A one hot value is encoded on the data bus in response to a low data rate. An XOR operation is performed with a previous state of the data bus and the encoded one hot value. Additionally, a resulting value of the XOR operation is driven onto the data bus.

Transition-minimized low speed data transfer

An electronic processing system may include a processor and a multi-level memory coupled to the processor, the multi-level memory including at least a main memory and a fast memory, the fast memory having relatively faster performance as compared to the main memory. The system may further include a fast memory controller coupled to the fast memory and a graphics controller coupled to the fast memory controller. The fast memory may include a cache portion allocated to a cache region to allow a corresponding mapping of elements of the main memory in the cache region, and a graphics portion allocated to a graphics region for the graphics controller with no corresponding mapping of the graphics region with the main memory.

Operating system transparent system memory abandonment

Integrated circuits, systems and methods are disclosed in which data bits protected by error correction code (ECC) detection and correction may be increased such that a combination of primary and additional bits may also be ECC protected using existing ECC allocation, without affecting ECC capabilities. For example, the additional bits may be encoded into phantom bits that are in turn used in combination with the primary bits, to generate an ECC. This ECC may then be combined with the primary bits to form a code word. The code word may be transmitted (or stored) so that when the data bits are received (or retrieved), assumed values of the phantom bits may be decoded, using the ECC, back into the additional bits without the phantom bits or the additional bits ever having transmitted (or stored).

Use of error correcting code to carry additional data bits

A method and apparatus are described for a shared LRU policy between cache levels. For example, one embodiment of the invention comprises: a level N cache to store a first plurality of entries; a level N+1 cache to store a second plurality of entries; the level N+1 cache to initially be provided with responsibility for implementing a least recently used (LRU) eviction policy for a first entry until receipt of a request for the first entry from the level N cache at which time the entry is copied from the level N+1 cache to the level N cache, the level N cache to then be provided with responsibility for implementing the LRU policy until the first entry is evicted from the level N cache, wherein upon being notified that the first entry has been evicted from the level N cache, the level N+1 cache to resume responsibility for implementing the LRU eviction policy with respect to the first entry.

Technology for an apparatus is described. The apparatus can include a plurality of cache memories and a cache controller. The cache controller can allocate a cache entry to store data across the plurality of cache memories. The cache entry can include a value in a metadata field indicating an interleave policy. The cache controller can selectively assign the interleave policy to be applied based on a type of data stored in the plurality of cache memories.

Selevtive application of interleave based on type of data to be stored in memory

Integrated circuits are provided which create page locality in cache controllers that allocate entries to set-associative cache, which includes data storage for a plurality of Sets of Ways. A plurality of cache controllers may be interleaved with a processor and device(s), and allocate to any pages in the cache. A cache controller may select a Way from a Set to which to allocate new entries in the set-associative cache and bias selection of the Way according to a plurality of upper address bits (or other function). These bits may be identical at the cache controller during sequential memory transactions. A processor may determine the bias centrally, and inform the cache controllers of the selected Set and Way. Other functions, algorithms or approaches may be chosen to influence bias of Way selection, such as based on analysis of metadata belonging to cache controllers used for making Way allocation selections.

Systems and methods for improving write-back cache performance by utilizing scrubbed state indicators associated with the cache entries. The example system may comprise: a cache comprising a plurality of cache entries; a processing core, coupled to the cache; and a cache controller configured to maintain a plurality of indicators corresponding to a plurality of cache entries, wherein each indicator of the plurality of indicators indicates whether a corresponding cache entry has been scrubbed by synchronizing the cache entry with a next level memory after the cache entry has been modified.

Growing community of inventors

Jerusalem, Israel

Daniel Greenspan