Xilinx, Inc.

Tabula, Inc.

Xilinix, Inc.

Daniel Gitlin

Michael J Hart

Shahin Toutounchi

James Karp

Martin L Voogel

Xin X Wu

Jongheon Jeong

Deepak K Nayak

Hsung Jai Im

Boon Yong Ang

Sunhom Paak

Yuhao Luo

Sheau-suey Li

Kameswara K Rao

Kevin T Look

Shuxian Wu

Jae-Gyung Ahn

Radko Gerard Bankras

Stephen M Trimberger

Steven P Young

Jason Rupert Redgrave

Jan Lodewijk De Jong

Michael G Ahrens

Hua Shen

Shih-Cheng Hsueh

Tiemin Zhao

Xiao-Jie Yuan

Matt Crowley

Dennis L Segers

Some embodiments provide an integrated circuit ('IC') that includes at least first and second circuits operating at a first voltage. The IC includes, between the first and second circuits, a direct connection comprising a third circuit for transmitting a signal from the first circuit to the second circuit at a second voltage that is lower than the first voltage. At least one of the first and second circuits is a configurable circuit for configurably performing operations.

Method and apparatus for saving power in an integrated circuit

A circuit for protecting a transistor during the manufacture of an integrated circuit device is disclosed. The circuit comprises a transistor having a gate formed over an active region formed in a die of the integrated circuit device; a protection element formed in the die of the integrated circuit device; and a programmable interconnect coupled between the gate of the transistor and the protection element, the programmable interconnect enabling the protection element to be decoupled from the transistor.

Circuit for protecting a transistor during the manufacture of an integrated circuit device

An MOS device has an embedded dielectric structure underlying an active portion of the device, such as a source extension or a drain extension. In an alternative embodiment, an embedded dielectric structure underlies the channel region of a MOS device, as well as the source and drain extensions.

Semiconductor device with backfilled isolation

An electrically erasable programmable read-only memory ('CMOS NON-VOLATILE MEMORY') cell is fabricated using standard CMOS fabrication processes. First and second polysilicon gates are patterned over an active area of the cell between source and drain regions. Thermal oxide is grown on the polysilicon gates to provide an isolating layer. Silicon nitride is deposited between the first and second polysilicon gates to form a lateral programming layer.

Method of fabricating CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer

A method of protecting a transistor formed on a die of an integrated circuit is disclosed. The method comprises forming an active region of the transistor on the die; forming a gate of the transistor over the active region; coupling a primary contact to the gate of the transistor; coupling a programmable element between the gate of the transistor and a protection element; and decoupling the protection element from the gate of the transistor by way of the programmable element. Circuits for protecting a transistor formed on a die of an integrated circuit are also disclosed.

Method of and circuit for protecting a transistor formed on a die

CMOS-compatible non-volatile memory cell with lateral inter-poly programming layer

A MOS transistor is used as a programmable three-terminal non-volatile memory element. The gate dielectric layer of the MOS transistor has a first portion with a relatively higher dielectric breakdown strength than a second portion. The location of the second portion is chosen so as to avoid having the gate dielectric layer break down near the edge of the active area or isolation area during programming. In a particular embodiment, the gate dielectric layer is silicon oxide, and the first portion is thicker than the second portion.

Three-terminal non-volatile memory element with hybrid gate dielectric

A method for dealing with process specific physical effects applies dimensional modifications to an IC layout to compensate for performance variations caused by the physical effects. Because the dimensional modifications harmonize the performance of the actual IC with the performance of the IC model, time-consuming re-verification operations are not required. Current drive variations caused by shallow trench isolation (STI) stress can be compensated for by adjusting the gate dimensions of the affected transistors to increase or decrease current drive as necessary. Such physical effect compensation can be applied before, after, or even concurrently with optical proximity correction (OPC). The dimensional modifications for physical effect compensation can also be incorporated into an OPC engine.

Layout correction algorithms for removing stress and other physical effect induced process deviation

A transistor with ballast resistor formed between the transistor drain and the drain contact is formed by masking regions of the ballast resistor to increase resistivity and thus reduce required area. The invention achieves this without introducing any additional process or masking steps. Thus the invention allows a reduction in IC die size for the same ESD requirement or allows better ESD protection for a given die size.

Ballast resistor with reduced area for ESD protection

An ESD protection circuit includes a bipolar transistor, a resistor, and a zener diode formed on and within a semiconductor substrate. The resistor extends between the base and emitter regions of the transistor so that voltage developed across the resistor can turn on the transistor. The zener diode is formed in series with the resistor and extends between the base and collector regions of the transistor. Thus configured, breakdown current through the zener diode, typically in response to an ESD event, turns on the transistor to provide a nondestructive discharge path for the ESD. The zener diode includes anode and cathode diffusions. The cathode diffusion extends down into the semiconductor substrate in a direction perpendicular to the substrate. The anode diffusion extends down through the cathode diffusion into the semiconductor substrate. The anode diffusion extends down further than the cathode diffusion so that the zener diode is arranged vertically with respect to the substrate. The cathode diffusion can be formed using two separate diffusions, one of which extends deeper into the substrate than other.

Method of forming a zener diode

Structures and methods for selectively applying a well bias to only those portions of a PLD where such a bias is necessary or desirable, e.g., applying a positive well bias to transistors on critical paths within a user's design. A substrate for an integrated circuit includes a plurality of wells, each of which can be independently and programmably biased with the same or a different well bias voltage. In one embodiment, FPGA implementation software automatically determines the critical paths and generates a configuration bitstream that enables positive well biasing only for the transistors participating in the critical paths, or only for programmable logic elements (e.g., CLBs or lookup tables) containing those transistors. In another embodiment, negative well biasing is selectively applied to reduce leakage current.

Structures and methods for selectively applying a well bias to portions of a programmable device

Memory cell structures and related circuitry for use in non-volatile memory devices can be fabricated utilizing standard CMOS processes, for example, 0.18 micron or 0.15 micron processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials, for example, between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming.

Non-volatile memory array using gate breakdown structures

Memory cell structures and related circuitry for use in non-volatile memory devices are described. The cell structures can be fabricated utilizing standard CMOS processes, e.g. sub 0.35 micron or sub 0.25 micron processes. Preferably, the cell structures can be fabricated using 0.18 micron or 0.15 micron standard CMOS processes. Advantageously, the cell structures can be programmed so that a conductive path is formed between like type materials. For example, in certain cell structures a cell is programmed by applying a programming voltage in such a way as to form a conductive path between a p-type gate and a p-type source/drain region or an n-type gate and an n-type source/drain region. Programming cells in this manner advantageously provides a programmed cell having a low, linear resistance after programming. In addition, novel charge pump circuits are provided that, in a preferred embodiment, are located &ldquo;on chip&rdquo; with an array of memory cells. These charge pump circuits are preferably fabricated utilizing the same standard CMOS processing techniques that were utilized to form the memory cell structures and related circuitry.

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Palo Alto, CA, United States of America

Daniel Gitlin