International Business Machines Corporation

Synopsys, Inc.

Other

Marvell Semiconductor Israel Ltd.

Daniel Geist

Ohad Shacham

Rachel Tzoref

Mark Ginzburg

Yoad Lustig

Ishai Rabinovitz

Boris Gommershtadt

Shmuel Ur

Eitan D Farchi

Alexander Rabinovitch

Kenneth Nagin

Alan Hartman

Dmitry Korchemny

Yael Shaham-Gafni

Raanan Gewirtzman

Karen Holtz

Ilya Kudryavtsev

Paul Regis Kram

Nathaniel Azuelos

Yoon Kah Leow

Dmitriy Mosheyev

Srivatsan Raghavan

Ishai Rabinovotz

Alex Shot

Orna Grumberg

Richard Yachyang Sun

Sagi Katz

Monica Farkas

The independent claims of this patent signify a concise description of embodiments. A method is provided for reducing a size of an emulation clock tree for a circuit design. The method comprises identifying a fan-in cone of an input of a sequential element of the circuit design; identifying one or more fan-in cone sequential elements which do not directly affect the input of the sequential element; and removing the one or more identified fan-in cone sequential elements of the fan-in cone from the emulation clock tree. This Abstract is not intended to limit the scope of the claims.

Method and system for emulation clock tree reduction

A search for a regular expression in a tree hierarchy, includes, in part, searching for a match to the regular expression in a first subtree defined by a first node name, recording information about the first subtree if there is no match, determining whether a second subtree defined by a second node name is identical to the first node, skipping search of the second subtree if the second subtree is determined to be identical and prefix equivalent, with respect to the regular expression, to the first subtree. The second subtree is determined to be prefix equivalent to the first subtree when for any string s, a first prefix defined by a concatenation of the first node name and the string s results in a match if and only if a second prefix defined by a concatenation of the second node name and the string s results in a match.

Speeding matching search of hierarchical name structures

The independent claims of this patent signify a concise description of embodiments. A method of performing hardware emulation of a circuit design is presented. The method includes partitioning a first portion of the circuit design to a first configurable logic chip of a hardware emulator, adding a selection circuit to the circuit design in the first configurable logic chip, and selecting one of a first signal or a second signal during a first clock cycle. The first signal and the second signal are used in the circuit design. The method further includes storing a first value associated with the selected signal during a second clock cycle, and sending the first value to an output pin of the first configurable logic chip during a third clock cycle. This Abstract is not intended to limit the scope of the claims.

Adding delay elements to enable mapping a time division multiplexing circuit on an FPGA of a hardware emulator

Configuring a hardware system includes providing a first data representative of a first assignment of a multitude of wires to a multitude of physical connections between a multitude of logic circuits of the hardware system, and transforming the first data into a second data representative of a second assignment of the multitude of wires to the multitude of physical connections. The transforming includes calculating a multitude of latencies each associated with a selected one of the multitude of wires, and assigning a first subset of the multitude of wires to at least one of the multitude of physical connections in accordance with a first improvement goal. The transforming causes the value of each one of the multitude of latencies that are associated with the first subset to be less than or equal to the first improvement goal, when the second data is used to configure the hardware system.

Incrementally distributing logical wires onto physical sockets by reducing critical path delay

A computer-implemented method, apparatus and computer program product for debugging programs, the method comprising: displaying a graphic waveform showing values of one or more state variables of a computer program being debugged in two or more points in time; receiving a user selection from points in time, of an indication to a selected point in time in execution from the graphic waveform; and resuming within a debugger an execution state of the computer program associated with the selected point in time.

Method and apparatus for debugging programs

Systems and methods that use a solver to find bugs in a target model of a computing system having one or more finite computation paths are provided. The bugs on computation paths of less than a predetermined length are detected by translating the target model to include a state variable AF for one or more states of the target model, wherein AF(S) represents value of the state variable AF at state S; and solving the translated version of the target model that satisfies predetermined constrains.

Satisfiability (SAT) based bounded model checkers

A method uses a SAT solver operating to cycle k to find bugs in a model having finite computation paths therein, wherein said bugs are on computation paths of less than length k. Another method includes adding an additional state variable to a model to be checked, where a governing state machine of the additional variable has a 'sink' state. The method includes having a translation using the additional variable whenever a state indicates a bad state and performing satisfiability solving with the model and the translation.

A test coverage tool provides output that identifies differences between the actual coverage provided by a test suite run on a program under test and the coverage criteria (e.g., the coverage criteria required by the test/development team management). The output from the test coverage tool is generated in the same language that was used to write the coverage criteria that are input to an automated test generator to create the test cases which form the test suite. As a result, the output from the coverage tool can be input back into the automated test generator to cause the generator to revise the test cases to correct the inadequacies. This allows iterative refinement of the test suite automatically, enabling automated test generation to be more effectively and efficiently used with more complex software and more complex test generation inputs. In preferred embodiments, test coverage analysis results of several different test suites, some manually generated and others automatically generated, are used to produce a streamlined automatically-generated test suite and/or to add missing elements to an automatically generated test-suite.

Method and system for integrating test coverage measurements with model based test generation

A method for verification includes providing an implementation model, which defines model states of a target system and model transitions between the model states, and providing a specification of the target system, including properties that the system is expected to obey. A tableau is created from the specification, the tableau defining tableau states with tableau transitions between the tableau states in accordance with the properties. The tableau transitions are compared to the model transitions to determine whether a discrepancy exists therebetween.

Identification of missing properties in model checking

A synchronization method including running a system ( ) having multiple agents ( and ) in parallel operation, the multiple agents each having at least one path ( ) to a common bus ( ). A bus arbitration mechanism ( ) is used to synchronize between said multiple agents in accordance with a predetermined scheme, including blocking ( ) at least one individual agent's path to the common bus ( ) if said scheme indicates ( ) that said individual agent is not to be activated, and restoring ( ) said at least one individual agent's path ( ) to the common bus ( ) once said scheme indicates that said individual agent ( ) can be activated.

Synchronization using bus arbitration control for system analysis

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Haifa, Israel

Daniel Geist