Ip-first, LLC

Integrated Device Technology, Inc.

Daniel G Miner

G Glenn Henry

Arturo Martin-de-Nicolas

Brian Snider

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program by inserting the test parameters in place of a plurality of non-specific test operands. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

Apparatus and method for testing memory in a microprocessor

An apparatus and method are provided for testing memory circuits in a microprocessor. The apparatus includes test management logic and test execution logic located within the microprocessor. The test management logic has a non-specific test program stored therein, and it accepts test parameters provided by an external test controller. The test parameters are applied to the non-specific test program to produce a specific test program. The test execution logic executes the specific test program to test the memory circuits within the microprocessor at the internal speed of the microprocessor.

Apparatus for testing memory in a microprocessor

An apparatus and method for smart configuration of functional blocks within a semiconductor device is provided. A fuse array contains a plurality of fuses that are blown in manufacturing to enable/disable functional blocks on the semiconductor device. A control unit reads the state of the fuses, and logically merges the fuse states with a default configuration for the functional blocks. The result of the merge operation is stored in a feature control register that individually enables/disables the functional blocks. The control unit also receives a write command from an external source that modifies the feature control register, after the device is shipped from the manufacturer. The control unit selectively blocks writes to the feature control register that attempt to enable/disable functional blocks that should not modified.

Fuse array control for smart function enable

A method and apparatus for testing redundant circuitry within a memory array is provided. A control unit is described to interface a memory array to a wafer tester to selectively enable redundant rows/columns within a memory array during wafer test, without requiring permanent alteration of row/column select switches. Temporary enabling of redundant rows/columns allows testing of redundancy prior to alteration of the permanent switch logic. The control unit, upon command from a wafer tester, selectively enables particular redundant rows/columns to allow those redundant rows/columns to be tested. After testing, if the redundant rows/columns repair memory defects, permanent switch logic may be altered, without requiring further testing of the redundant circuitry.

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Austin, TX, United States of America

Daniel G Miner