Intel Corporation

Daniel G Borkowski

Krishnakanth Venkata Sistla

Avinash N Ananthakrishnan

Ankush Varma

Vivek Garg

Ian M Steiner

Matthew M Bace

Mark Rowland

Kirk S Yap

Dean A Mulla

Shahrokh Shahidzadeh

Vasudevan Srinivasan

Sergiu D Ghetie

Niall D McDonnell

Neeraj S Upasani

Samie B Samaan

Stephanie L Hirnak

Manev Luthra

Victor J Wu

Vijaya K Boddu

Won Lee

Muthu Venkatachalam

Kenneth Young

Chelsea Akturan

Cagdas Akturan

Ronan D O'Ceallaigh

Nancy S Borkowski

Victor Wu

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory. For instance, there is disclosed in accordance with one embodiment a functional semiconductor package, including: a processor core configurable via a plurality of configuration registers; a non-volatile storage, in which a first portion of the non-volatile storage includes permanently lockable storage that once written cannot be overwritten or modified, and in which a second portion of the non-volatile storage includes the plurality of configuration registers; a first write interface to the non-volatile storage, in which the permanently lockable storage of the non-volatile storage is wirelessly writable externally from the functional semiconductor package via the first write interface; a second write interface to the non-volatile storage through which the plurality of configuration registers are writable; configuration data for the processor core written wirelessly into the permanently lockable storage of the non-volatile storage; and in which the configuration data is distributed into the plurality of configuration registers via the second write interface at every boot of the functional semiconductor package. Other related embodiments are disclosed.

Systems, methods, and apparatuses for implementing late fusing of processor features using a non-volatile memory

In one embodiment, a processor includes: a first die including at least one processor core to execute instructions and a non-volatile storage to store an identifier to be provisioned into the processor during manufacture; a second die to couple to the first die, the second die including a wireless circuit and a second non-volatile storage; and a wireless interface to couple to the second die to enable wireless communication with a wireless device. The processor may be disabled if the identifier is not stored in the second non-volatile storage. Other embodiments are described and claimed.

System, apparatus and method for securely protecting a processor in transit

In one embodiment, the present invention includes a multicore processor having a power controller with logic to dynamically switch a power management policy from a power biased policy to a performance biased policy when a utilization of the processor exceeds a threshold level. Thus at low utilizations, reduced power consumption can be realized, while at higher utilizations, greater performance can be realized. Other embodiments are described and claimed.

Dynamically modifying a power/performance tradeoff based on a processor utilization

Systems and methods may provide for determining, in a first domain that manages a state of a second domain, that the second domain is in the state and determining, in the first domain, that a periodic action has been scheduled to occur in the second domain while the second domain is in the state. Additionally, the periodic action may be documented as a missed event with respect to the second domain. In one example, documenting the periodic action as a missed event includes incrementing a missed event counter.

Tracking missed periodic actions across state domains

A message channel optimization method and system enables multi-flow access to the message channel infrastructure within a CPU of a processor-based system. A user (pcode) employs a virtual channel to submit message channel transactions, with the message channel driver processing the transaction 'behind the scenes'. The message channel driver thus allows the user to continue processing without having to block other transactions from being processed. Each transaction will be processed, either immediately or at some future time, by the message channel driver. The message channel optimization method and system are useful for tasks involving message channel transactions as well as non-message channel transactions.

Virtualized communication sockets for multi-flow access to message channel infrastructure within CPU

Dynamically modifying a power/performance tradeoff based on processor utilization

A generic multi-stage nested hash unit that provides support for generic, multi-stage nested hashes accelerates a wide range of security algorithms and protocols. The supported security algorithms and protocols include SSL v3 MAC, TLS PRF, and SSL v3 Key Material Generation. The hash unit allows the same code to be used to generate the MAC even when the MAC algorithms are different, for example, for SSL and TLS protocols.

Method and apparatus for generic multi-stage nested hash processing

A method and apparatus to control interaction between two multi-threaded processor engines is presented. A first multi-threaded processor engine is configured for connection to a serial link, and performs receive and transmit operations in a first 'PHY' mode of operation. A second multi-threaded processor engine is operable to process data received by the first multi-threaded processor over the serial link and to provide the processed data to the first multi-threaded processor engine for transmission over the serial link, when the first multi-threaded processor operates in the PHY mode. Additionally, the first multi-threaded processor engine is configured to execute certain operations, e.g., hardware accelerator operations, at the request of the second multi-threaded processor engine in a second 'co-processor' mode of operation.

Microengine to network processing engine interworking for network processors

Systems and methods are disclosed for using High-level Data Link Control (HDLC) channel context information to simultaneously process multiple HDLC channels. Preferred embodiments of the present invention enable a single network processing engine to process multiple HDLC channels. The current state of the HDLC channel can be evaluated, stored, and restored, which means that the processing of a channel can be halted, the channel state read and stored, and the state of a different channel written to the processing engine. This allows the engine to begin processing a new channel, and then, at a later stage, restore the state of the original channel and resume processing.

Systems and methods for using HDLC channel context to simultaneously process multiple HDLC channels

A method and apparatus for remapping channel data are presented. Multiple successive frames carrying data in timeslots are received. The timeslots are assigned to channels so that data for the channels includes interleaved data. The data from the multiple successive frames for each of a predetermined number of the timeslots are aggregated. The aggregated data is mapped, by timeslot, to produce a timeslot-based map. The aggregated data of the timeslot-based map is remapped to produce a channel-based map in which the data for the channels are grouped together by channel in the order that the data were received.

Cycle-efficient TDM timeslot remapping for network processing engines

Growing community of inventors

Lunenburg, MA, United States of America

Daniel G Borkowski