Cirrus Logic Inc.

Daniel G Bezzant

Stephen A Smith

Arunachalam Vaidyanathan

Suhas Anand Shetty

Narasimha R Nookala

Ashutosh S Dikshit

Bryan Michael Richter

Jihad Y Abudayyeh

Kasturiraman Gopalaswamy

Puducode S Narayanan

Venkateswarrao Ketineni

Nagina Naresh Shetty

Ramprasad Rangarajan

Joseph Chacko

A PCMCIA host adapter includes the capability to master a non-DMA system bus and control a DMA data transfer between a DMA capable peripheral and the internal system memory. A peripheral can be coupled to the system through a PCMCIA card plugged into a PCMCIA expansion slot. A DMA controller coupled to the PCMCIA expansion slots through a PCMCIA bus controls a DMA transfer between the internal system memory and the peripheral. A bus master disables the CPU and takes control of the system bus during a DMA data transfer. In an alternative embodiment, the PCMCIA host adapter can be used with either a system having a system bus with DMA capability or with a system having a system bus without DMA capability. In this alternate embodiment if the system bus has DMA capability, the PCMCIA host adapter effectively passes the DMA signals between the peripheral and the system bus. If the system bus does not have DMA capability then the DMA controller and the bus master work to disable the CPU and take control of the system bus during a DMA data transfer. The DMA controller then controls the transfer of data between the peripheral and the internal system memory.

PCMCIA host adapter and method for variable data transfers

A clock frequency multiplier with a rise detector flip-flop connected to a series of buffers having interspersed parallel output taps connected to a binary to Gray converter for providing real time rise status indications. The parallel tap outputs are connected to first, second and third multiplexers, to produce first and second fall outputs and a second rise output. The multiplexers are controlled by first, second and third corresponding tap circuits having hexadecimal inputs from a Gray to hexadecimal converter connected to the output of the binary to Gray converter through a flip-flop clocked by a second rise of the input clock signal.

Digital clock frequency multiplication circuit and method

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Alternatively communication between an expansion board and a socket controller may be performed across a cable separate from the hard disk drives having a different signal line format. The system adapter may be included within a single interface expansion board which can be connected to the motherboard and CPU system bus or it can be directly connected or soldered to the motherboard and communicate with the socket controller and ATA hard disk drives using one or more busses.

Method and apparatus for interfacing between peripherals of multiple

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software that was written for previous hardware. Versions of software written for previous hardware attempt non-native register accesses for which the integrated circuit is designed to emulate the non-native register set. Versions of software specifically written for the present hardware attempt native register accesses for which no emulation is necessary. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode the interrupt information is written to an appropriate register and then mapped into the appropriate bits of the physical register set. In the second mode the interrupt information is written directly to the appropriate register. In both the first and second modes, steering bits from the appropriate register are used to map system, management and wakeup interrupts to the appropriate interrupt pad where the interrupt request signal is then shaped.

Method and apparatus for providing register and interrupt compatibility

An apparatus for providing register compatibility between integrated circuits having different register and interrupt configurations is designed to operate with software. Software may attempt non-native register accesses; the integrated circuit of the present invention will emulate a non-native register set. In the preferred embodiment only one physical register set is included on the integrated circuit and a compatibility engine is used when a non-native register access is attempted. The compatibility engine is coupled between a bus interface unit and the physical register set and allows a user or system designer to address a register set of another integrated circuit having a different configuration than the physical register set. The compatibility engine converts the address and maps the data bits of the emulated register into registers within the physical register set. Alternatively, two sets of registers can be physically included on the integrated circuit. An interrupt compatibility circuit is also designed to operate in at least a first mode or a second mode. In the first mode, the interrupt information is written to an appropriate register and then mapped into appropriate bits of the physical register set. In the second mode, interrupt information is written directly to the appropriate register.

Method and apparatus for providing register compatibility between

A peripheral interface system and apparatus including a pair of integrated circuits, referred to as a system adapter and a socket controller, use a communication protocol, referred to as a windowed-interchip-communication protocol, to interface peripherals, such as PCMCIA cards or infrared devices, and other subsystems having different formats with a CPU system bus. The system adapter communicates to a hard disk drive subsystem using the ATA communication standards to interface an ATA hard disk drive with the CPU system bus. Communication between the system adapter and the socket controller, which communicates with PCMCIA peripheral cards and IR peripherals, is accomplished using the windowed-interchip-communication protocol which may share hardware resources with other communication protocols. Communication between the system adapter and the hard disk drive and between the system adapter and the socket controller may be provided on the same chain of a standard 40 signal ribbon cable. Status detection logic circuitry is included within the socket controller for detecting changes in status of selected signals and notifying the system adapter of the changes in status. This status detection logic circuitry ensures that multiple changes of status of the selected signals are recorded and reported to the system adapter in the order in which the changes occurred.

A host adapter of a computer system includes combinational logic circuit eliminating both positive and negative-glitches from an input signal. The circuit comprises two NAND gates and two delay elements in one embodiment. The delay introduced by second delay element is twice that of the first delay element. The first delay element receives as input the input signal. The first NAND gate receives as inputs the input signal and the output of the first delay element. The second delay element receives as input the output of the first NAND gate. The second NAND gate receives as inputs the output of the first NAND gate and the output of the second delay element. The output of the second NAND gate comprises the input signal with both positive and negative glitches having a duration of less than the delay of the first delay element eliminated. In a second embodiment, the two NAND gates are replaced by two NOR gates.

Combinational logic circuit, system and method for eliminating both

A device for use in a computer system, particularly a personal computer (PC) which provides compatibility for a proposed ISA plug and play (PNP) standard. The device of the present invention is also backward compatible with non-PNP (legacy) PCs. Upon power-up, a device may initialize using default traditional or specification (ISA) values for I/O address, IRQ and DMA channels. If PNP activity by the host PC is detected by the device, the device is disabled, and awaits activation and I/O address, IRQ and DMA channel assignments from a host PC. If no PNP activity by a host PC is detected, the device continues to operate using default traditional or specification (ISA) I/O address, IRQ and DMA channels. The device of the present invention may be installed in PNP or legacy type PCs without reconfiguring hardware (e.g., DIP switches, jumpers or the like) in the device or installing new firmware, operating system, or applications software in a host PC.

Growing community of inventors

Pleasanton, CA, United States of America

Daniel G Bezzant