Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Daniel Edward Tuers

Abhijeet Manohar

Yehuda Hahn

Yoav Weinberg

Dana Lee

Jonathan Hsu

Grishma Shah

Sergey Anatolievich Gorobets

Henry Chin

Hua-Ling Cynthia Hsu

Nicholas Thomas

Yosief Ataklti

Chris Avila

Gautam Ashok Dusija

Sahil Sharma

Eran Erez

YenLung Li

Gary Lin

Joseph Robert Meza

Girish Desai

Min Peng

Matthew Davidson

Milton Lourenco Barrocas

Abjiheet Manohar

Nian Niles Yang

Menahem Lasser

Jianmin Huang

Man Lung Mui

Andrew John Tomlin

Mark Murin

Xinde Hu

Tien-Chien Kuo

Anubhav Khandelwal

Mark Shlick

Cynthia Hsu

Gadi Vishne

Dmitry Vaysman

Steven S Cheng

Reed P Tidwell

Yuri Ryabinin

Vered Kelner

Dennis S Ea

Noga Deshe

Anne Pao-Ling Koh

Yiwei Song

Sathyanarayanan Subramanian

Robert Jackson

Venkata Krishna Nadh Dhulipala

Tienchien Kuo

Eakta Anchila

Leonid Romanovsky

Raja Alwar Gopinath

Nurit Appel

Sujeeth Joseph

Thomas Ta

Abhijeet Mahohar

Nathaniel Deneui

Vijay Motagi

Akshay Naik

Upon detecting power loss during the process of programming multi-level cell (MLC) memory in a storage system, the storage system takes steps to prevent data loss. In one example, the controller sends a graceful shutdown command to the memory, in response to which the memory aborts the ongoing programming operation and stores data from data latches associated with unprogrammed memory cells in single-level cell (SLC) memory. The memory can also store data from programmed memory cells in the SLC memory. The data to be programmed in the MLC memory can be reconstructed prior to powering down the storage system or after the storage system is powered back up. The reconstructed data can then be programmed in the MLC memory.

Storage system and method for data protection during power loss

A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.

Overhead reduction in data transfer protocol for NAND memory

The present disclosure generally relates to optimizing device interrupt coalescing based upon host device behavior. The data storage device maintains three functional states: a training state, a holding state, and a retraining state. The data storage device switches between states based upon host device behavior as well as the behavior of the data storage device. Once the data storage device finds the optimum conditions for coalescing, the data storage device will periodically test the conditions to adapt to changing host device behavior as well as data storage device behavior. In so doing, the data storage device can dynamically adjust interrupt coalescing to ensure optimum operation of the storage device.

Device interrupt coalescing with various host behaviors

The present disclosure generally relates to thermal throttling a nonvolatile memory device in a data storage device. Nonvolatile memory devices can sustain higher temperatures for a limited duration of time as part of the lifecycle/operation of the device. By allowing for a small margin of time at a higher temperature of operation, the maximum capability of the data storage device is increased. In so doing, the data storage device reliability can be maintained while increasing the device performance.

SSD operation in a nonoptimal memory environment

A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.

Inherent adaptive trimming

Systems, methods, and apparatus are provided that can reduce power consumption of memory controllers in response to memory command backlog in various situations. A data storage device includes a plurality of sets of non-volatile memory (NVM) devices, a central controller, and a plurality of channel controllers. Each channel controller is coupled to a distinct set of the plurality of sets of NVM devices. Each channel controller includes a command queue configured to store pending memory commands and provide backlog information. The central controller is configured to receive the backlog information of the command queues of the plurality of channel controllers, and adjust a clock frequency of the central controller and one or more clock frequencies of the plurality of channel controllers based on the backlog information such that the pending memory commands in each of the command queues are below a predetermined threshold level.

Reactive power management for non-volatile memory controllers

A controller of a non-volatile memory system may be configured to identify bits of data to be stored in memory elements of non-volatile memory that are identified as unreliable. The controller may be configured to bias at least some of these bits to a predetermined logic value at which the bits are likely to be read from the unreliable memory elements. The controller may do so using a biasing key that the controller generates based on identification of the bits. Subsequently, when the data is read, the controller may assign log likelihood ratio values for the bits to correspond to a percent likelihood of the bits being biased to the predetermined logic value. The bits may also be unbiased using the biasing key.

Biasing schemes for storage of bits in unreliable storage locations

The subject matter described herein includes processing file system metadata in host write requests to determine information about future host write operations. The information regarding future host write operations can be used by a device controller to prepare the non-volatile memory for the future host write operations. For example, the device controller may prepare the non-volatile storage device for future sequential host write access patterns or random host write access patterns depending on the content of the file system metadata. The file system metadata may also be usable to determine when it is optimal to perform memory management operations.

Storage devices and methods for optimizing use of storage devices based on storage device parsing of file system metadata in host write operations

A non-volatile memory system may include a write task queue that queues write commands and a garbage collection module that analyzes information about pending write commands in the write task queue in order to perform garbage collection. Based on its analysis of the write task queue, the garbage collection module performs discouraging actions to discourage itself from selecting certain blocks in a candidate list to be source blocks for garbage collection. In addition or alternatively, the garbage collection module performs encouraging actions to encourage itself to select blocks storing current valid data associated with a write command as source blocks for garbage collection. Write amplification may be reduced as a result of the discouraging and encouraging actions.

Garbage collection based on queued and/or selected write commands

A cluster association recognition system and related method are described. The system may identify sequences of data clusters in compilations of cluster journals. The system may generate the compilations by populating the cluster journals with cluster identifications associated with host addresses identified in host read requests. Upon receipt of future read requests, the cluster sequences may be used to identify data sets that are associated with a cluster sequence in order to identify further data sets that a host is likely to request.

Self-describing cluster association

A memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment are provided. In one embodiment, a memory die is provided comprising a memory array, an interface, at least one register, and circuitry. The circuitry is configured to receive, via the interface, a pause command from a controller in communication with the memory die; and in response to receiving the pause command: pause a data transfer between the memory die and the controller; and while the data transfer is paused and until a resume command is received, maintain state(s) of the at least one register irrespective of inputs received via the interface that would otherwise change the state(s) of the at least one register. Other embodiments are provided.

Memory system and method for simplifying scheduling on a flash interface module and reducing latencies in a multi-die environment

A storage device utilizing read look ahead (RLA) may utilize auxiliary or spare latches as a RLA cache for storing pre-fetch data. The RLA may predict the next commands and do a speculative read to the flash using the latches for RLA storage. The auxiliary/spare latches may be present on a plane or die of non-volatile memory and may be different from the transfer data latch (XDL) that transfers data from the memory and the host. When the XDL is backed up, sense commands may still be performed and the data is stored in the auxiliary latches before being transferred with the XDL.

Preserving read look ahead data in auxiliary latches

A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.

Memory system and method for reducing read disturb errors

Methods, systems, and computer readable media for automatically deriving hints from storage device accesses and from file system metadata and for utilizing the hints to optimize utilization of the memory storage device are provided. One method includes analyzing an input/output operation involving non-volatile memory or file system metadata. The method further includes automatically deriving, based on results from the analyzing, a hint regarding an expected access pattern to the non-volatile memory. The method further includes using the hint to optimize utilization of the non-volatile memory.

Methods, systems, and computer readable media for automatically deriving hints from accesses to a storage device and from file system metadata and for optimizing utilization of the storage device based on the hints

Growing community of inventors

Kapaa, HI, United States of America

Daniel Edward Tuers