Google Inc.

Other

Daniel Earle Gibson

Monica C Wong-Chan

Milo Martin

Dennis Charles Abts

Simon Luigi Sabato

Joel Scherpelz

Aspects of the disclosure relate to providing derived keys for connectionless network protocols. The derived key may be provided by receiving, at a host, a remote procedure call (RPC) sent by a remote host in response a request by an application executing on the remote host. The host may generate a derived key from a region key, the region key being associated with an application-specific memory region on the host. The host may transmit the derived key to the remote host.

Derived keys for connectionless network protocols

Network protocols generally implement integrity protection, encryption and authentication as separate validation steps. Since each validation step contributes encoding and processing overhead associated with individual packet transfers over the network, such network protocols can make inefficient use of limited packet space. Systems and methods according to the present disclosure combine integrity protection, encryption and authentication into a single validation step thereby making efficient use of limited packet space.

Combined integrity protection, encryption and authentication

System utilization related to memory usage can be monitored by storing host memory usage information in the corresponding host physical memory. However, retrieving this information can be a high overhead operation because it involves engaging with the operating system of each host. Moreover, storing memory usage information in the host physical memories can pose a security risk if they also store privileged data. Network interfaces according to the present disclosure provide unobtrusive and secure support for monitoring of network and other system resources such as regions of memory within host physical memories. Implementations according to the present disclosure include a plurality of memory region counters stored on a network interface. Each memory region counter corresponds to one of the memory regions located in a physical memory of a host coupled to the network interface. Each of the counters includes a system utilization metric associated with its corresponding memory region.

Unobtrusive support for third-party traffic monitoring

The location of the memory controllers within the on-chip fabric of multiprocessor architectures plays a central role in latency bandwidth characteristics of the processor-to-memory traffic. Intelligent placement substantially reduces the maximum channel load depending on the specific memory controller configuration selected. A variety of simulation techniques are used along and in combination to determine optimal memory controller arrangements. Diamond-type and diagonal X-type memory controller configurations that spread network traffic across all rows and columns in a multiprocessor array substantially improve over other arrangements. Such placements reduce interconnect latency by an average of 10% for real workloads, and the small number of memory controllers relative to the number of on-chip cores opens up a rich design space to optimize latency and bandwidth characteristics of the on-chip network.

Method for optimizing memory controller placement in multi-core processors by determining a fitness metric based on a bottleneck link in a multiprocessor array

Method for optimizing memory controller placement in multi-core processors using a fitness metric for a bit vector of EAH memory controller

Method for optimizing memory controller configuration in multi-core processors using fitness metrics and channel loads

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Madison, WI, United States of America

Daniel Earle Gibson