Hewlett-packard Company

Advanced Micro Devices Corporation

Globalfoundries Inc.

Daniel E Yee

Byron Alan Alcorn

Ted B Ziemkowski

Gregory A Hill

David Jarosh

A method and processor are provided. The method includes storing a first value at a first field of a first cache tag line when a next occurrence of a first COF instruction is presumed to branch and when the end location of the first COF instruction is at a first location of memory, storing a second value at the first field to indicate the next occurrence of the first COF instruction is presumed to branch and when the end location of the first COF instruction is at a second location of memory. The processor includes an instruction cache having instruction data represented by a plurality of data segments and a prefetch unit. The prefetch unit is operable to receive a first data segment from the instruction cache and determine whether an end byte of a predicted taken COF instruction is present in the first data segment.

System and method for aligning change-of-flow instructions in an instruction buffer

A cache memory comprising: 1) a tag array comprising a plurality of tag entry locations that are accessed by R of the M least significant bits of an N-bit received address and stored an address tag comprising the (N-M) most significant bits of the N-bit received address. The cache memory also comprises 2) cache hit comparison circuitry for comparing the (N-M) most significant bits of an N-bit received address with an address tag and generating a HIT signal if a match occurs, and 3) tag array test circuitry for testing the operation of the tag array and the cache hit comparison circuitry.

Built-in self test circuit for testing cache tag array and compare logic

Method and apparatus for synchronizing vertical refresh and the display of left versus right channels in a stereoscopic, multi-display computer graphics system. Each graphics pipeline in the system is coupled to its own synchronization controller. The synchronization controllers each have a synchronization input and a synchronization output. The inputs and outputs are coupled in series to form a daisy chain. One of the synchronization controllers is designated the master, the rest are slaves. The master generates a signal that transitions when the master enters vertical front porch. The slaves pass this signal down the daisy chain. Each slave will wait at the end of its own vertical front porch for a transition on the signal. When the transition occurs, the slave immediately enters vertical sync. If no transition occurs within a predetermined time, the slave will enter vertical sync at the end of the predetermined time. The state of the synchronization signal is used by each graphics pipeline to determine which channel, left or right, will be displayed during the upcoming frame.

Synchronization of left/right channel display and vertical refresh in

A bidirectional asynchronous open collector buffer. The buffer employs set delays and control logic to prevent latch up of the buffer when the low signal is applied to one of the ports of the buffer. Additionally, the buffer employs reset delays in conjunction with the control logic for suppressing oscillation of the buffer when one of the ports of the buffer is released from the applied low signal.

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Loveland, CO, United States of America

Daniel E Yee