Tandem Computers Incorporated

Daniel E Lenoski

Peter L Fu

David J Garcia

Leonard E Overhouse

Albert Jordan

A synchronous processor unit is divided into two sections, and each separately clocked by different clock signals. One section, containing an instruction execution unit and memory for storage of instructions and data, is clocked at a higher frequency, while the other section, containing those elements of a processor unit less frequently used, are clocked with a slower-frequencied clock. The elements of each section are intercoupled by separate and independent data buses, and selectively to one another by a buffer unit. The clock signals used by both sections are produced by a clock-generating unit which also monitors the instructions being executed by the instruction execution unit. When an instruction requiring communication between the two sections is detected, at least one predetermined transition of each of the fast and slow clocks are synchronized, and during this synchronization the separate buses of each section are coupled to one another by the buffer unit for information exchanges therebetween.

Synchronous processor unit with interconnected, separately clocked

A method and mechanism for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

System to determine if modification of first macroinstruction to execute

A system for folding the address space of a reserved segment of a high speed memory into a designated part of the address space of a cache memory included in the high speed memory. Folding information for distinguishing between cache entries that have been folded from reserved segments and those that normally map into a designated segment of the high speed memory is stored. The folding information is utilized to determine whether a cache miss occurs when the designated segment of the cache memory is accessed.

System for cache space allocation using selective addressing

A fixed entry-point map to produce an entry point address of a first micro-instruction for a particular macro-instruction. That address is then incremented by a fixed number to produce the second, third, etc. micro-instructions for that macro-instruction. In a first embodiment, after a fixed number of these address skips, the addresses are incremented by 1 so that successive micro-instructions are in adjacent address locations. In a second embodiment, the number of skips is variable.

Entry point mapping and skipping method and apparatus

A method and mechanism operate for shortening the execution time of certain macro-instructions by looking at both a present macro-instruction and a next macro-instruction. The invention includes two, interrelated aspects for accomplishing this. First, a first operation of a next macro-instruction is performed concurrently with a last operation of a current macro-instruction. Second, the next macro-instruction is decoded to determine the minimum number of clock cycles it requires. If this minimum number is below a specified number, the micro operations of the present instruction are modified to perform appropriate set-up operations for the next macro-instruction to enable it to be completed in the computed minimum number of clock cycles.

Method and apparatus for modifying micro-instructions using a

A stack with a unary encoded stack pointer which uses the position of a single bit to point to the top of the stack. A number of multi-bit latches are used to store the data elements in the stack. A serial, bidirectional shift register is loaded with all digital zeros except for a position having a digital one (the pointer) which is coupled to the register containing the top of the stack. As new data elements are pushed onto or popped off of the top of the stack, the pointer is shifted right or left accordingly.

Stack with unary encoded stack pointer

A cross-coupled checking circuit is disclosed in which two identical integrated circuit chips are configured in a complementary manner and connected in parallel to the same inputs and outputs. One chip drives the data output data and the other chip drives the check symbol output corresponding to the output data. Each chip generates internal results and compares them to the output driven by the other chip.

Cross-coupled checking circuit

A processor system utilizing a single shared RAM array, for storing microcode and other function data, with the shared array coupled to the processor by a single shared ADR/DATA bus. In one embodiment, an onboard ROM stores selected lines of microcode and a ROM accessing system supplies microcode from the ROM when the shared RAM array is busy performing some other RAM function.

Microcoded microprocessor with shared ram

An address generation system that generates a second address relative to a first address by either incrementing, decrementing, or passing unchanged, as determined by the control digits in a LIT field, the digital number encoded by the most significant bits of the first address and substituting a selected subset of the digits in the LIT field for the least significant bits of the first address. The first address may be the program counter address and the second address the target address of a branch instruction.

System for performing group relative addressing

A level sensitive scan design (LSSD) diagnostic apparatus for a data processing component. Each scan unit in a shift register chain comprises a plurality of level sensitive elements, e.g., data latches, which transfer signals from their input terminals to their output terminals in response to a 'Phase B' pulse train. A multiplexer is connected to each data latch for communicating run data to the input terminal of each data latch in a normal mode of operation. In test mode, the multiplexer communicates signals from the output terminal of one data latch to the input terminal of an adjacent data latch, so that the data latch signals are serially communicated through the resulting latch chain. In order to prevent the test data from propagating uncontrollably through the serially connected latches, each multiplexer includes a test latch disposed between the test data input of the multiplexer and the output terminal of the preceding data latch in the chain. The test latch is controlled by a 'Phase A' pulse train signal which is interleaved with the phase B pulse train.

Growing community of inventors

Mountain View, CA, United States of America

Daniel E Lenoski