Infineon Technologies Ag

Infineon Technologies Austria Ag

Daniel Domes

Franz-Josef Niedernostheide

Reinhold Bayerer

Mark-Matthias Bakran

Zheming Li

Robert Maier

Roland Rupp

Holger Ruething

Patrick Baginski

Franz Hirler

Anton Mauder

Ralf Otremba

Johannes Georg Laven

Roman Baburske

Thomas Basler

Uwe Jansen

Christian Robert Mueller

Andreas Lenniger

Patrick Jones

Waleri Brekel

Stefan Hubert Schmies

Andreas Groove

Matthias Wissen

Jens De Bock

Bjoern Rentemeister

Andreas Vetter

Wolfgang Budde

Andressa Colvero Schittler

Andre Lenze

Christian Robert MÜLLER

Maximilian Slawinski

Switch modules, driver circuits for switch modules and corresponding methods are provided. In an implementation, a switch module includes a transistor switch including a control terminal, a first load terminal and a second load terminal, and a short circuit detection circuit configured to detect a short circuit state between the first load terminal and the second load terminal and to electrically couple the control terminal and the first load terminal in response to detecting the short circuit state. The short circuit detection circuit is supplied by a voltage between the control terminal and the first load terminal.

Switch module, driver circuit and related methods

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to control a gate voltage to generate an on-current during a plurality of turn-on switching events to turn on the transistor. The gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage, and a second driver configured to, during a boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage. A control circuit measures a transistor parameter representative of a reverse recovery current of the transistor for a turn-on switching event during which the transistor is transitioned to an on state and controls the first driver and controls the second driver based on the measured transistor parameter.

Actively tracking switching speed control and regulating switching speed of a power transistor during turn-on

A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between first and second terminals, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. One first diode is electrically coupled in parallel to each switching device of the first type. One second diode is electrically coupled in parallel to each switching device of the second type. The switching devices are arranged in a power semiconductor module having first and second longitudinal sides and first and second narrow sides. The first type switching devices and first diodes are arranged alternatingly in one row along the first longitudinal side. The second type switching devices and second diodes are arranged alternatingly in another row along the second longitudinal side. An axis of symmetry that extends perpendicular to the first and second narrow sides.

Semiconductor arrangements

A semiconductor module arrangement includes a housing, a first semiconductor substrate arranged inside the housing, a second semiconductor substrate arranged inside the housing, a first plurality of controllable semiconductor elements, and a second plurality of controllable semiconductor elements. During operation of the semiconductor module arrangement, each controllable semiconductor element of the first plurality of controllable semiconductor elements generates switching losses and conduction losses, the switching losses being greater than the conduction losses. Further during operation of the semiconductor module arrangement, each controllable semiconductor element of the second plurality of controllable semiconductor elements generates switching losses and conduction losses, the conduction losses being greater than the switching losses. At least a first sub-group of the first plurality of controllable semiconductor elements is arranged on the first semiconductor substrate, and at least a first sub-group of the second plurality of controllable semiconductor elements is arranged on the second semiconductor substrate.

Semiconductor module arrangement

An electronic device includes: an interface configured to receive telemetry information for one or more power semiconductor devices; and a data acquisition and processing unit. The data acquisition and processing unit may be configured to periodically update an estimate of a remaining lifetime of the one or more power semiconductor devices, based on the telemetry information collected during use of the one or more power semiconductor devices and received at the interface. The data acquisition and processing unit may be configured to adjust one or more operating parameters for each of the one or more power semiconductor devices that has reached a predetermined level of degradation as determined by the telemetry information. An electronic system that includes the electronic device is also described.

Electronic device and electronic system that receives and processes telemetry information

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

Method for reducing oscillation during turn on of a power transistor by regulating the gate switching speed control of its complementary power transistor

A gate driver system includes a gate driver circuit coupled to a gate terminal of a transistor and configured to generate an on-current during a plurality of turn-on switching events to turn on the transistor, wherein the gate driver circuit includes a first driver configured to source a first portion of the on-current to the gate terminal to charge a first portion of the gate voltage and a second driver configured to, during a first boost interval, source a second portion of the on-current to the gate terminal to charge a second portion of the gate voltage; a measurement circuit configured to measure a transistor parameter indicative of an oscillation of a load current for a turn-on switching event; and a controller configured to receive the measured transistor parameter and regulate a length of the first boost interval based on the measured transistor parameter.

A method is provided for driving a half bridge circuit that includes a first transistor and a second transistor that are switched in a complementary manner. The method includes generating an off-current during a plurality of turn-off switching events to control a gate voltage of the second transistor; measuring a transistor parameter of the second transistor during a first turn-off switching event during which the second transistor is transitioned to an off state, wherein the transistor parameter is indicative of an oscillation at the first transistor during a corresponding turn-on switching event during which the first transistor is transitioned to an on state; and activating a portion of the off-current for the second turn-off switching event, including regulating an interval length of the second portion for the second turn-off switching event based on the measured transistor parameter measured during the first turn-off switching event.

A semiconductor module arrangement includes a housing and at least one pair of semiconductor substrates arranged inside the housing. Each pair of semiconductor substrates includes first and second semiconductor substrates. The first semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The second semiconductor substrate includes a first dielectric insulation layer arranged between a first metallization layer and a third metallization layer, and a second dielectric insulation layer arranged between the third metallization layer and a second metallization layer. The third metallization layer of the first semiconductor substrate is electrically coupled to a first electrical potential, and the third metallization layer of the second semiconductor substrate is electrically coupled to a second electrical potential that is opposite to the first electrical potential.

A semiconductor arrangement includes at least two switching devices of a first type electrically coupled in parallel between a first terminal and a second terminal, and at least two switching devices of a second type electrically coupled in parallel between the second terminal and a third terminal. The switching devices of the first type and the switching devices of the second type are arranged in a power semiconductor module that has first and second longitudinal sides and first and second narrow sides. The switching devices of the first type and the switching devices of the second type are arranged next to each other in at least one row extending in a first horizontal direction that is parallel to the first and second longitudinal sides, such that within each of the at least one rows no more than two switching devices of the same type are arranged in direct succession.

A method of driving a transistor includes generating an off-current during a plurality of turn-off switching events to control a gate voltage at a gate terminal of the transistor, wherein generating the off-current includes sinking a first portion of the off-current from the gate terminal to discharge a first portion of the gate voltage, and sinking, during a boost interval, a second portion of the off-current from the gate terminal to discharge a second portion of the gate voltage; measuring a transistor parameter indicative of an oscillation of a drain-source voltage of the transistor for a first turn-off switching event during which the transistor is transitioned off; activating the first portion of the off-current for a second turn-off switching event; and activating the second portion of the off-current for the second turn-off switching event, including regulating a length of the boost interval based on the measured transistor parameter.

Actively tracking switching speed control of a power transistor

A power semiconductor arrangement includes a plurality of half-bridges arranged in parallel alongside one another by way of a longer longitudinal side of the half-bridges. An input load current terminal, an output load current terminal and a phase terminal are arranged on a top side of each of the half-bridges, the input load current terminals and the output load current terminals being arranged on an imaginary line that runs orthogonal to the longer longitudinal side of the half-bridges. First connection plates are connected to respective ones of the output load current terminals, and second connection plates are connected to respective ones of the input load current terminals. The first connection plates are arranged above the second connection plates. The first and the second connection plates are arranged in parallel with one another and electrically insulated from one another.

Power semiconductor arrangement having a stack of connection plates

An electric assembly includes a bipolar switching device and a transistor circuit. The transistor circuit is electrically connected in parallel with the bipolar switching device and includes a normally-on wide bandgap transistor.

Electric assembly including a bipolar switching device and a wide bandgap transistor

A multiplicity of power semiconductor switching elements of the same type parallel have a load current terminal for a load current input and a load current terminal for a load current output. At least one outer load current terminal and at least one inner load current terminal per load current direction include a load current input and a load current output. At least one contacting device for common electrical contacting all of the load current terminals of the same load current direction includes a load current input and a load current output. The contacting device includes a plurality of terminal tongues which are respectively fastened on an associated load current terminal. The geometry and/or profile of the terminal tongue of an outer load current terminal differs from the geometry and/or profile of the terminal tongue of an inner load current terminal of the same contacting device.

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Ruethen, Germany

Daniel Domes