Maxim Integrated Products, Inc.

Motorola Corporation

Daniel David Alexander

Daniel James Miller

David J Anderson

David Castaneda

Jason Ryan Ferguson

Yuanfang Li

Brian A Miller

Feihua Zhang

Yassar Ali

David Maes

Timothy Lance Blankenship

Syed Aftab

Chad Thomas Steward

Jiuhui Wang

Daniel J Black

Hang Fung Yip

Andrew Chan

Syed Amir Aftab

Described herein are systems and methods for real-time fault detection in electrical circuits. Various embodiments provide a fault detection circuit that uses a resistor network that is controlled to detect an internal current leak in multiple directions, e.g., to ground or to a power supply. The magnitude of the leakage current may be estimated from voltage measurements at voltage pins. In addition, as part of circuit diagnostics, open and short circuit fault conditions may be identified by using current sources and measuring deflections at the voltage pins.

Systems and methods for real-time fault detection

An analog front-end circuit for self-calibrating a comparator, the circuit comprising a comparator in a comparator measurement path; a preamplifier coupled to the comparator by a set of switches; and an amplifier coupled to the preamplifier, the preamplifier receiving a reference signal as a first input and a user-definable reference as a second input, the user-definable reference generating a user-definable value chosen to create a known condition at an output of the preamplifier, the preamplifier determines a residual value that represents a measurement error in a signal path comprising the comparator and is used to adjust the user-definable reference value to calibrate the signal path such that threshold boundaries for the comparator can be adjusted to tighten a comparator specification.

Comparator diagnostic systems and methods

Described are systems and methods take advantage of properties of sinc filters that remove frequency components at specific integer multiples of a noise frequency. In various embodiments, sampling of multi-channel systems at sufficiently high rates allows for removal of unwanted signals and harmonics from multi-sample sequences. Advantageously, a multi-sample sequence scheduling scheme eliminates the need for noise filtering one channel at a time at each channel's own sampling rate using a separate filter.

Systems and methods for on-chip filtering

System and method for substantially reducing an involvement of an applications processor in receiving data from a touchscreen display. In one aspect, the system includes a controller may be configured in an autonomous mode where it automatically measures the touchscreen display based configuration information received from the applications processor, determines notable events based on the measurement data, stores data and event identifiers related to the notable events in a memory, and sends a notification to the applications processor when event data is available In another aspect, the system includes a controller that filters user interactions events and transmits data related to only notable events to the applications processor. Because of the autonomous and event filtering operations of the touchscreen controller, there are substantially less communications between the controller and the applications processor. This improves the speed and efficiency of the applications processor.

System and method for interfacing applications processor to touchscreen display for reduced data transfer

An N bit sub-binary radix digital-to analog converter (DAC) includes a radix conversion module that converts an m bit digital input signal to an N bit sub-radix DAC code. A ladder module having NL bits has a plurality of first circuit elements corresponding to first respective bits of the N bit sub-radix DAC code. A segment module having NS bits has at least one second circuit element corresponding to second respective bits of the N bit sub-radix DAC code. N&#x3e;m, and N is the sum of NL and NS.

[object Object]

A system includes an N bit sub-binary radix digital-to-analog converter (DAC) that converts an m bit digital input signal to an analog output signal, where m and N are integers greater than or equal to 1 and N&#x3e;m. A radix conversion module determines a code ratio, the code ratio being a ratio of a total number of available monotonic codes to 2, and performs radix conversion on the m bit digital input signal based on the code ratio.

High speed digital path for successive approximation analog-to-digital converters wherein the successive approximation registers and the switch drivers are combined in set-reset latches having the switch drivers as latch outputs. This reduces the time of each successive approximation by reducing the ripple through time of each stage, thereby increasing the speed of operation of the analog-to-digital converters. As an option, the set-reset latches having the switch drivers as latch outputs may also incorporate level shifting to combine each stage of the successive approximation register, associated switch drivers and level shifters into a single circuit for each stage of the analog-to-digital converter. Various embodiments are disclosed.

High speed digital path for successive approximation analog-to-digital converters

A device and technique for selective over-ranging provides for the folding of signals in an input signal range such that the folded signals in the center of the input signal range are folded N times while the folded signals at the lower and upper extremes of the input signal range are folded NF &plus;1 times. One embodiment includes an over-ranging lower pre-amplifier group ( ), a center pre-amplifier group ( ) and an over-ranging upper pre-amplifier group ( ).

Selective over-ranging in folding and averaging integrated circuits

A switched capacitor differential comparator (10) for receiving input signals which includes hysteresis circuitry (40, and 42) and a switch (43) responsive to timed clocking pulses occurring during alternating reset and comparison periods for application of a hysteresis current during a reset period of the differential comparator which current is injected into an applicable one of a pair of load devices (22, 24) to produce a hysteresis voltage offset at a selected one of the differential inputs (30, 32) which is stored during the reset period but removed during the next comparison period so that the hysteresis voltage is not canceled but remains superimposed on the stored input signals during the next comparison period to introduce hysteresis to influence the current output decision of the comparator circuit based on the decision of the comparator resulting from the previous comparison period.

Precision hysteresis circuit

A circuit and method control the common-mode potential at an output (17, 18) of a fully differential amplifier (32) by feeding forward a common-mode correction signal through the amplifier. An input signal (V.sub.IN+ -V.sub.IN-) is amplified in the amplifier to produce a differential output signal (V.sub.O- -V.sub.O+) at the output. A common potential of the differential inputs (37, 38) of the amplifier is sensed with a transistor (54, 56) biased to a reference voltage (V.sub.CM) and amplified through the amplifier to produce a common-mode correction signal to offset a common-mode component of the differential output signal. A feedback circuit (33-36) is used to develop the common potential from the common-mode component.

Amplifier with input referred common-mode adjustment

A comparator (12) and method compare first and second signals (V.sub.IN+, V.sub.IN-) to provide an output signal (V.sub.O, V.sub.OB). A transistor (43) couples a supply terminal (64, 66) of the comparator to a power supply (V.sub.DD) to enable the comparator for comparing the first and second signals. When the output signal is valid, it turns off the transistor to isolates the supply terminal from the power supply. As a result, power is reduced and a change in the first and second signals is prevented from changing the output signal. When the transistor turns off, a charge is trapped on the supply terminal that unbalances the comparator and causes a comparison error. A balanced condition is restored with a discharge circuit (31-33) coupled to the supply terminal to alter the charge when a control signal (RESET) is applied.

Growing community of inventors

Gilbert, AZ, United States of America

Daniel David Alexander