National Semiconductor Corporation

Daniel D Culmer

Ronald W Russell

Robert A Cometta

James B Compton

Thomas M Frederiksen

Walter R Davis

Sam S Ochi

Harry J Bittner

Adib R Hamade

A differential amplifier is combined with a latch in a stage suitable for use in high speed comparators. An IC topography for the latch is also shown.

Bipolar strobed transistor latch for a high gain comparator

An integrated circuit includes a plurality of circuit elements interconnected to operate as a circuit and formed in a common semiconductor substrate. The substrate is mounted on a supporting package, resulting in a mechanical stress in the substrate which is symmetrical about at least one given axis. At least the circuit elements with operating characteristics which are altered by the mechanical stress and which have a critical matching or ratio relationship are arranged symmetrically about the stress axis of symmetry. In a preferred form, the integrated circuit is a linear circuit, such as an operational amplifier employing junction field effect transistors (JFETs) for its input stage and bipolar transistors for its amplifier stage. Providing device symmetry about an axis of mechanical stress symmetry enables shifts in input offset voltage for such operational amplifiers to be reduced up to a factor of about 10.

Stress insensitive integrated circuit

A linear amplifier output stage is provided with unity gain buffer means having an input coupled to the output terminal and an output coupled to the stage input. The unity gain buffer means is normally turned off by a control signal. When the amplifier is disabled by switching its bias current off, the buffers are turned on so that the output stage input capacitance is charged or discharged via the buffer means in accordance with the output terminal signal. When a plurality of such amplifiers are commonly coupled to a signal line the off amplifiers cannot be driven into conduction by the operating amplifier's output signal.

Bistate linear amplifier circuit

An element of an integrated circuit, such as an ion implanted region or a metal layer, may be laser trimmed without exposing P-N junctions or other circuit elements not to be trimmed to damage by the laser through use of the present protection process and structure. In the process, an oxide through which the laser trimming is carried out is formed over a selected portion of the circuit to be trimmed by the laser. A bare layer of a metal reflective to the laser radiant energy beam, such as aluminum, gold or silver, is formed surrounding the selected portion of the circuit. The selected portion of the integrated circuit is then trimmed with the laser. The oxide promotes trimming in the selected area by absorbing the laser radiant energy beam. The bare metal layer protects the portion of the integrated circuit underlying it by reflecting most of its energy.

Laser trim protection process and structure

A MOSFET switching device, including first and second control terminals; a first MOSFET having its gate connected to the first control terminal; a second MOSFET having its gate connected to the second control terminal and its source and drain both connected to the source of the first MOSFET; and a third MOSFET having its gate connected to the second control terminal and its source and drain both connected to the drain of the first MOSFET. When complementary control signals are applied to the first and second control terminals, charge spikes occurring at the source and drain of the first MOSFET when the conduction state of the first MOSFET is changed are cancelled by charge spikes occurring simultaneously in the second and third MOSFET's.

MOSFET switching device with charge cancellation

An expanded analog-to-digital converter includes a first digital-to-analog converter for converting the most significant bits of digital output signal having a given number of bits to a first analog reference signal having a value that is proportional to the value of the most significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is other than zero; and a second digital-to-analog converter for converting the least significant bits of the digital output signal to a second analog reference signal. A successive approximation register successively provides the bits of a digital output signal in accordance with a comparison of an analog input signal with the sum of the analog reference signals. A logic circuit coupled to the successive approximation register for providing an indication of whether the value of the most significant bits is other than zero, causes the second analog reference signal to have a value that is proportional to the value of the least significant bits whenever the value of the most significant bits is other than zero, and a value that is proportional to the value of the least significant bits minus one-half the least significant bit of the digital output signal whenever the value of the most significant bits is zero.

Expanded analog-to-digital converter having one-half LSB shift

Laser trim protection process

A pair of transistors are operated at different current densities so as to develop a differential base to emitter potential. This potential is used as a reference in a negative feedback stabilization circuit which passes a current that is regulated by the potential. The circuit can also regulate the currents flowing in a plurality of additional current sources and sinks connected thereto.

Constant current control circuit

A system for establishing a precise reference current and steering the precise reference current through a load. A reference resistance is connected between a first node and a common terminal and a first reference voltage is maintained at the first node to establish a precise current flow through the reference resistance. A capacitance is connected between the source and the gate of a field effect transistor. A first switch is provided for connecting the field effect transistor in series with the reference resistance. A control loop is connected to a second node in the series circuit between the first switch and the field effect transistor and to a second reference voltage terminal. A second switch is provided for connecting the control loop to the gate of the field effect transistor; and a third switch connected to the second node is provided for connecting the field effect transistor in series with a load. When the first and second switches are closed and the third switch is open, the control loop causes the capacitance to be charged until the voltage at the second node matches the second reference voltage to thereby provide a voltage across the gate and source of the field effect transistor for sustaining the flow of the precise current through the reference resistor. When the first and second switches are opened and the third switch is closed, the charge on the capacitance causes the precise current to continue to flow from the field effect transistor and the third switch steers the current through the load.

System for establishing and steering a precise current

A base junction transistor inverter circuit will be driven into the saturation region if the drive current is large enough. In such circumstances, the collector voltage can go below the base voltage and approaches the emitter voltage. A circuit is provided to keep the transistor out of saturation and is comprised of a p-channel field effect transistor (JFET) connected between the base and collector of the junction transistor. The JFET is connected such that when the drive current increases and the junction transistor approaches saturation, the drive current is diverted through the JFET and into the substrate. The same clamp can be implemented by using a pnp junction transistor in combination with an n-channel JFET.

JFET base junction transistor clamp

An analog switching circuit employs a field effect transistor as a switching element and a regulation circuit for maintaining the bias on the FET constant with changes in the amplitude of an analog signal in the circuit being controlled. The regulation circuit includes a current source, a pair of elements for generating a voltage drop connected in parallel with one another and in series with the current source, and a circuit for maintaining the voltage drops in those circuit elements equal to one another. The circuit elements are connected in series with one another between the source and the gate of the FET, such that the bias on the FET remains constant. A control circuit is operative to disrupt the balance of currents in the circuit elements to cause the FET to become nonconductive.

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Sunnyvale, CA, United States of America

Daniel D Culmer