Intel Corporation

Other

Daniel Cummings

Hieu T Ngo

Glenn E Starnes

Amir Javidi

Juan Pablo Munoz

Anthony Sarah

Mohammed Hasan Taufique

Shantanu Ganguly

Elliot R Lang

Tristan Webb

Sharath Nittur Sridhar

Jacqueline S Nelson

Louis J Wither

Maciej Szankin

Souvik Kundu

The present disclosure is related to machine learning model swap (MLMS) framework for that selects and interchanges machine learning (ML) models in an energy and communication efficient way while adapting the ML models to real time changes in system constraints. The MLMS framework includes an ML model search strategy that can flexibly adapt ML models for a wide variety of compute system and/or environmental changes. Energy and communication efficiency is achieved by using a similarity-based ML model selection process, which selects a replacement ML model that has the most overlap in pre-trained parameters from a currently deployed ML model to minimize memory write operation overhead. Other embodiments may be described and/or claimed.

Machine learning model scaling system with energy efficient network data transfer for power aware hardware

The present disclosure is related to framework for automatically and efficiently finding machine learning (ML) architectures that are optimized to one or more specified performance metrics and/or hardware platforms. This framework provides ML architectures that are applicable to specified ML domains and are optimized for specified hardware platforms in significantly less time than could be done manually and in less time than existing ML model searching techniques. Furthermore, a user interface is provided that allows a user to search for different ML architectures based on modified search parameters, such as different hardware platform aspects and/or performance metrics. Other embodiments may be described and/or claimed.

Framework for optimization of machine learning architectures

Described is apparatus comprising a first circuitry, a second circuitry, and a third circuitry. The first circuitry may have an output coupled to a shared-read-data signal path, and the first circuitry either driving its output to a value based on a sensed memory bit, or not driving its output. The second circuitry may have a first clocked inverter and a second clocked inverter cross-coupled with the first clocked inverter, an input of the first clocked inverter being coupled to the shared-read-data signal path, and an output of the first clocked inverter being coupled to an inverse-data signal path. The third circuitry may have an inverter with an input coupled to the inverse-data signal path and an output coupled to a data signal path.

Area-efficient scalable memory read-data multiplexing and latching

Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.

SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter

Embodiments of an apparatus and method to improve power delivery including a pre-charge circuit that may include a first voltage supply rail configured to provide a first voltage amount to perform a first phase of a pre-charge of a bit line and a second voltage supply rail configured to provide a second voltage amount to perform a second phase of the pre-charge of the bit line are described herein. In embodiments, the pre-charge circuit may be a pre charge circuit for a static random-access memory (SRAM) memory cell.

Apparatus and method for improving power delivery in a memory, such as, a random access memory

A coil unloading and transporting apparatus is disclosed and is suited for unloading coiled aluminum and other metals from a storage shaft and moving the coils from the storage shaft to a pallet for further transport. The unloading and transporting apparatus comprises a carriage movable from a position adjacent the storage shaft to a position remote from the storage shaft. A platform for supporting the coil is mounted on the carriage and a receiving shaft extends outwardly from the platform. The storage shaft can be withdrawn below the plane of the platform. The platform and the receiving shaft is pivotal from a position wherein the receiving shaft is horizontal and the coil is supported on the receiving shaft to a position wherein the receiving shaft is vertical and the coil is supported on the platform. Once the coil is supported on the platform, the receiving shaft may be withdrawn below the platform, and the coil transported by the carriage to a remote location.

Growing community of inventors

Austin, TX, United States of America

Daniel Cummings