International Business Machines Corporation

Daniel Cocanougher

Robert K Montoye

Stephen Larry Runyon

Myhong Nguyenphu

Peter W Markstein

A method for performing floating point division is provided for producing a quotient having a mantissa of n bits. The method consists of the steps of accessing an initial guess of a reciprocal of the divisor from a table of divisor reciprocals, computing an initial estimate the quotient in a corresponding estimate from the initial estimate of the reciprocal, increasing the precision of the mantissa of the reciprocal estimate, quotient estimate, and remainder estimate by computing an error parameter and iteratively computing a current reciprocal estimate, a current quotient estimate and a current remainder estimate from the error parameter and the latest reciprocal estimate, quotient estimate and remainder estimates. Also, the step of increasing the precision is repeated until the quotient estimate and reciprocal estimate exceed n bits. Lastly, the final quotient is computed from the last current quotient estimate plus the last current reciprocal estimate times the last current remainder estimate. A floating point apparatus is also provided that implements the floating point division method. The application of this method and apparatus provide a quotient result that is correctly rounded without conditionally testing the magnitude of the quotient.

Method and apparatus for performining floating point division

A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

Floating point arithmetic two cycle data flow

A processor for performing floating point arithmetic operations is provided that includes a circuit that performs a first floating point arithmetic operation on a set of operands in a first cycle and a second floating point arithmetic operation on an operand and a result of the first floating point arithmetic operation during a second cycle. A control circuit is provided for, in a third cycle, transferring a result of the second floating operation to the first floating point circuit for a first floating point operation in a next successive cycle while rounding the result of the second floating point operation.

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Fort Worth, TX, United States of America

Daniel Cocanougher