International Business Machines Corporation

Daniel Citron

Moshe Klausner

Itzhack Goldberg

Aviad Zlotnick

Yaakov Yaari

Ayal Zaks

Marcel Zalmanovici

Yarden Nir-Buchbinder

Yousef Shajrawi

Aharon Kupershtok

Dorit Nuzman

Testing a computer program comprises identification of resource access requests by the computer program to a resource provided by an underlying host. The resource access requests may be intercepted and a determined response may be returned instead of the actual response of the underlying host. In some exemplary embodiments, the resource may a clock of the underlying host and the response may be the time of the clock. In some exemplary embodiments, the computer program may be tested to check for validity during execution on a cloud computing environment, in which access to resources may yield results that on a non-cloud computing environments are generally not expectable. The testing may be performed on a non-cloud computing environments and simulate scenarios applicable to cloud computing environments.

Verification of a computer program in respect to an unexpected response to an access request

A dedicated vector gather buffer (VGB) that stores multiple cache lines read from a memory hierarchy in one or more Logical Units (LUs) each having multiple buffer entries and performs parallel operations on vector registers. Once loaded with data, an LU is read using a single port. The VGB initiates prefetch events that keep it full in response to the demand created by 'gather' instructions. The VGB includes one or more write ports for receiving data from the memory hierarchy and a read port capable of reading data from the columns of the LU to be loaded into a vector register. Data is extracted from the VGB by (1) using a separate port for each item read, (2) implementing each VGB entry as a shift register and shifting an appropriate amount until all entries are aligned, or (3) enforcing a uniform offset for all items.

Vector gather buffer for multiple address vector loads

Systems and methods for cache optimization are provided. The method comprises tracing objects instantiated during execution of a program code under test according to type of access by one or more threads running in parallel, wherein said tracing provides information about order in which different instances of one or more objects are accessed by said one or more threads and whether the type of access is a read operation or a write operation; and utilizing tracing information to build a temporal relationship graph (TRG) for the accessed objects, wherein the objects are represented by nodes in the TRG and at least two types of edges for connecting the nodes are defined.

Detecting and optimizing false sharing

A novel and useful apparatus for and method of associating a dedicated coverage bit to each instruction in a software system. Coverage bits are set every time the software application runs, enabling a more comprehensive and on-going code coverage analysis. The code coverage bit mechanism enables code coverage analysis for all installations of a software application, not just software in development mode or at a specific installation. Code coverage bits are implemented in either the instruction set architecture (ISA) of the central processing unit, the executable file of a software application, a companion file to the executable file or a code coverage table residing in memory of the computer system.

Apparatus for and method of life-time test coverage for executable code

A method for transferring data from a general purpose register (GPR) to a vector register (VR), the method including vectorially combining data in the VR from the GPR, by executing instructions of a PowerPC Instruction Set Architecture (ISA), the step of combining including splatting a low nibble from the GPR into a low nibble in each element of a first VR by executing two 'load vector for shift left' (lvsl) or 'load vector for shift right' (lvsr) and one &#x201c;vector subtract unsigned byte modulo&#x201d; (vsububm), shifting a high nibble of the GPR into a low nibble the GPR, splatting the low nibble of the GPR into a low nibble in each element of a second VR by re-executing the two lvsl or lvsr and one vsububm instructions, shifting the low nibble of the second VR into a high nibble of the second VR and combining both first and second VRs into one VR.

Splat copying GPR data to vector register elements by executing lvsr or lvsl and vector subtract instructions

An integrated circuit device includes a processing component and a cache, which is arranged to store data for use by the processing component responsively to an addressing scheme based on memory addresses having an address length of ml bits. First and second buses are coupled between the processing component and the cache, the buses having bus widths of nand nbits, respectively, such that n&#x3c;m. The processing component and the cache each include a respective address bus expander coupled to the first bus in order to compact at least some of the memory addresses for transmission over the first bus so that each of the at least some memory addresses is transmitted over the first bus in one cycle of the first bus.

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Haifa, Israel

Daniel Citron