Intel Corporation

Micron Technology Incorporated

Daniel Chu

Raymond W Zeng

Kiran Pangal

Mase J Taub

Sandeep K Guliani

Rajesh Sundaram

Shekoufeh Qawami

Derchang Kau

Owen W Jungroth

Balaji Srinivasan

Doyle W Rivers

Lark-Hoon Leem

John Gorman

Nathan Franklin

Prashant S Damle

Gerald J Barkley

Koushik Banerjee

Bi Han

Shravya Gottipati

Hu Chaohong

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may include a plurality of local controllers that each independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands. The apparatus may include a controller to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

Apparatuses and methods for concurrently accessing multiple partitions of a non-volatile memory

Apparatuses and methods for performing multithread, concurrent access of different partition of a memory are disclosed herein. An example apparatus may include a non-volatile memory array comprising a plurality of partitions. Each of the plurality of partitions may include a respective plurality of memory cells. The apparatus may further include a plurality of local controllers that are each configured to independently and concurrently access a respective one of the plurality of partitions to execute a respective memory access command of a plurality of memory access commands responsive to receiving the respective memory access command. The example apparatus may further include a controller configured to receive the plurality of memory access commands and to determine a respective target partition of the plurality of partitions for each of the plurality of memory access commands. The controller may be further configured to provide each of the plurality of memory access commands to a local controller of the plurality of local controllers associated with the respective target partition.

Nonvolatile memory (e.g. phase change memory) devices, systems, and methods that minimize energy expenditure and wear while providing greatly improved error rate with respect to marginal bits are disclosed and described.

Dual demarcation voltage sensing before writes

Technology for a memory device is described. The memory device can include an array of memory cells and a memory controller. The memory controller can receive a request to program a memory cell within the array of memory cells. The memory controller can select one or more timing offsets for a programming pulse based on one or more of a polarity of access for the memory cell, a number of prior write cycles for the memory cell, or electrical distances between the memory cell and wordline/bitline decoders within the array of memory cells. The memory controller can initiate, in response to the request, the programming pulse with the one or more selected timing offset to program the memory cell within the array of memory cells.

Tailoring timing offsets during a programming pulse for a memory device

Nonvolatile memory (e.g. phase change memory) devices, systems, and methods of programming the nonvolatile memory including sensing of a snapback current using a set demarcation voltage for set bit mapped cells and a reset demarcation voltage for reset bit mapped cells before selective writes.

In one embodiment, an apparatus comprises read circuitry to apply a read voltage to a three dimensional crosspoint (3DXP) memory cell; and write setback circuitry to apply a first setback pulse having a first magnitude to the 3DXP memory cell in response to the application of the read voltage, wherein applying the first setback pulse comprises bypassing a current mirror that is to limit or control a magnitude of a second setback pulse applied to the 3DXP memory cell when the current mirror is coupled to the 3DXP memory cell.

Method and apparatus for multi-level setback read for three dimensional crosspoint memory

Technology for verifying cell programming for a phase change memory array is disclosed. In an example, a method may include sending a reset pulse to a phase change memory cell. The method may further include sensing a threshold voltage of the phase change memory cell in response to applying first and second verify voltages across the phase change memory cell, where the second verify voltage is lower than the first verify voltage. The method may also include determining whether the threshold voltage of the phase change memory cell was below the first or second verify voltages.

Cell programming verification

Technology for writing data to a phase change memory array is disclosed. In an example, a method may include identifying mask logic for masking cells in the phase change memory array and routing the mask logic to the cells. The method may further include routing input data to the cells. Set and reset pulses for the cells may be selectively prevented or inhibited based on the mask logic.

Phase change memory with mask receiver

Methods and systems for verifying cell programming in phase change memory

The present disclosure relates to mitigating read disturb in a cross-point memory. An apparatus may include a memory controller configured to select a target memory cell for a memory access operation. The memory controller includes a sense module configured to determine whether a snap back event occurs during a sensing interval; and a write back module configured to write back a logic one to the memory cell if a snap back event is detected.

Mitigating read disturb in a cross-point memory

A multi-die memory package may have separate chip enable inputs for the respective memory dice. Individual chip enable inputs may be separated by other chip connections such as power and ground. The memory dice may include multiple chip enable inputs to allow easy wire bonding of the individual chip enable inputs to a die without requiring any jumpers within the package. Circuitry may be included so that undriven chip enable inputs are masked and driven chip enable inputs may be propagated to the memory die to enable memory accesses while a single chip enable input is only connected to the capacitance of a single bonding pad.

Growing community of inventors

Folsom, CA, United States of America

Daniel Chu