Cisco Technology, Inc.

Violin Memory Inc.

Intel Corporation

Telefonaktiebolaget Lm Ericsson (publ)

Vsip Holdings LLC

Daniel Christian Biederman

Frederick Roland Schindler

Jon C R Bennett

Kenneth Coley

Matthew James Webb

Li-Jau Yang

David M Smith

Haichuan Tan

Howard Borchew

Senthil Arumugam

Malathy Sethuraman

Jeffrey P Chou

Aniket A Aphale

Norman William Finn

Constantine P Sapuntzakis

Peter Geoffrey Jones

Robert G Hathaway

Hugh Barrass

Jose Niell

Amrik Singh Bains

Ravi Tangirala

Chih-Jen Chang

Edward Ho

Wing Cheung

Patrick Wang

Dennis Fahey

Krishna Kondaka

Darrell Rice Heflin

Afshin Ganjooi

Vivian W Chiang

Sharvil Desai

Jon CR Bennett

Halchuan Tan

Multi-port Media Control Channel (MAC) with flexible data-path width. A multi-port receive (RX) MAC block includes multiple RX ports and a plurality of RX circuit blocks comprising an RX MAC pipeline for performing MAC Layer operations on RX data received at the RX ports. The RX circuit blocks are connected with variable-width datapath segments, and the RX MAC block is configured to implement a multi-port arbitration scheme such as a TDM (Time-Division Multiplexed) scheme under which RX data received at a given RX port are forwarded over the variable-width datapath segments using datapath widths associated with that RX port. A multi-port transmit (TX) MAC block implementing a TX MAC pipeline comprising TX circuit blocks connected with variable-width datapath segments is also provided. The RX and TX MAC blocks include CRC modules configured to calculate CRC values on input data received over datapaths having different widths.

Multi-port media access channel (MAC) with flexible data-path width

A compute device can access local or remote accelerator devices for use in processing a received packet. The received packet can be processed by any combination of local accelerator devices and remote accelerator devices. In some cases, the received packet can be encapsulated in an encapsulating packet and sent to a remote accelerator device for processing. The encapsulating packet can indicate a priority level for processing the received packet and its associated processing task. The priority level can override a priority level that would otherwise be assigned to the received packet and its associated processing task. The remote accelerator device can specify a fullness of an input queue to the compute device. Other information can be conveyed by packets transmitted between and among compute devices and remote accelerator devices to assist in determining an accelerator to use or other uses.

Processor related communications

Techniques to operate a time division multiplexing (TDM) media access control (MAC) module include examples of facilitating use of shared resources allocated to ports of a network interface based on a time slot mechanism. The shared resources allocated to process packet data received or sent through the ports of the network interface.

Techniques to operate a time division multiplexing(TDM) media access control (MAC)

A network device in a network is provided that is configured to implement a process for modifying a timestamp in a packet that is a timing protocol packet. The timing protocol packet is encapsulated by a user data protocol (UDP) datagram, where the modified timestamp is written into the packet, but does not require a checksum of the UDP datagram to be changed. The process includes receiving a packet including a first timestamp over the network, receiving the first timestamp from the packet and a second timestamp to be written to the packet, and determining a third timestamp that is a modification of the second timestamp to be written to the packet, the third timestamp having least significant bits modified from the second timestamp such that the checksum of the UDP datagram is unchanged. The process writes the third timestamp into the packet and transmits the UDP datagram to the network.

Checksum friendly timestamp update

According to one aspect of the teachings herein, a method and apparatus predict a departure time of transmit data transmitted from a first network entity to a second network entity, determine a timing difference between a detected departure time and the predicted departure time of the transmit data that is was based on an estimated path delay of data transmission circuitry, and indicate the timing difference in further transmit data, e.g., to improve synchronization at the second network entity. In one or more embodiments, the timing difference is further used to compensate one or more timing operations at the first network entity, such as adapting one or more prediction parameters used by a departure-time prediction process.

Method and apparatus for compensating synchronization timing in a distributed timing network

A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module.

RAIDed memory system

Flash memory is subject to a wear out failure mechanism which may depend on the number of times each cell of the memory is programmed and erased. The higher the programming voltage used, the more rapidly the cell degrades. A system and method for reducing the average programming voltage for data sets is disclosed.

System and method of data storage in flash memory

A memory system having a plurality of modules operated so that a group of memory modules may operation in a RAID configuration having an erase hiding property. The RAID groups are mapped to areas of memory in each of the memory modules of the RAID group. More than one RAID group may be mapped to a memory module and the erase operations of the RAID groups coordinated such that the erase operations do not overlap. This may improve the utilization of a bus over which the memory module communicates with the controller. Where a memory module is replaced by a memory module having an increased storage capacity, the additional storage capacity may be mapped to an expanded logical address space.

Memory module virtualization

A memory system and a method for managing the system is described. The system is configured such a plurality of system controllers, which may be RAID controllers, receive requests from the external environment and distribute the requests to a plurality of memory modules such that data may be stored in the memory modules. A global sequence number is assigned to the data of a data stripe so that the operations related to the data stripe are performed in an ordered manner so that the data remains consistent. A plurality of system controllers may comprise a domain and access a plurality of memory controllers and a plurality of domains may include at least one common memory module. A plurality of groups of controllers may communicate with a switch or with a representative controller so as to coordinate the assignment of global sequence numbers.

Memory system management

In a memory system where memory units may be separated from each other so as to operate substantially independently, the coordination of related memory operations between such units may be by synchronization of an epoch of time and the start of an epoch of time with a common synchronization source. The source may be distributed directly to each of the memory modules of a memory unit, or through an intermediate synchronization circuit of a memory unit that is common to the modules. Where the data is stored as a RAID stripe on a plurality of synchronized modules, the read and write or erase operations performed by the modules may be arranged such that the write operations or erase operations may not substantially affect the ability to promptly read the stored data of a RAID stripe.

Synchronization of a dispersed RAID group

A method is performed in a power sourcing device (PSD). The method includes, for each of a plurality of powered devices (PDs) configured to time-varyingly draw power from the PSD, (a) receiving a set of power requirements for that PD, (b) assigning a set of amounts of power to be allocated to that PD, each assigned amount respectively indicating an assigned power allocation to that PD at a different time slot, and (c) during each time slot, providing an amount of power to that PD in accordance with the assigned amount. The set of power requirements includes (1) a plurality of different amounts of power to be drawn by the PD, each different amount of power being associated with an operational mode in which the PD can operate and (2) a policy indicating which operational mode the PD should operate in at different times.

Techniques for network-centric scheduled power provisioning

A method and apparatus for bidirectional provision of inline power over data telecommunications cabling permits power to be received at a local powered device (PD) from remote power sourcing equipment (PSE) via at least one conductor at a first time and power to be provided by the local device to a remote device or another device at a second different time.

Bidirectional inline power port

An apparatus for providing link layer security in a Physical Layer Transceiver (PHY) is disclosed. In one embodiment, the apparatus may comprise analog circuitry configured to interface with a data transmission medium, digital circuitry configured to interface with a Media Access Controller (MAC); and a crypto engine coupled to the digital circuitry. Single interface and multiple interface schemes are provided to control both PHY and crypto functions. Embodiments are disclosed where the PHY controls the crypto device, and where the crypto device controls the PHY.

Growing community of inventors

San Jose, CA, United States of America

Daniel Christian Biederman