Agere Systems Inc.

Qorvo Us, Inc.

Rf Micro Devices, Inc.

Daniel Charles Kerr

Alan Sangone Chen

Eric K Bolton

Michael Carroll

Julio C Costa

Amal Ma Hamad

George Adrian Maxim

Baker P Scott

Christian Rye Iversen

Ali Tombak

William A Russell

Roger W Key

Nace Rossi

Michael Scott Carroll

Mark Dyson

Thiet The Lai

Dirk Robert Walter Leipold

David C Dening

Edward T Spears

Hideya Oshima

Philip W Mason

Thomas Gregory Mckay

Edward Paul Martin, Jr

Joseph M Gering

Jinsung Choi

Thomas Craig Esry

Bradley J Albers

Robert Andrew Phelps

Roscoe T Luce

Michele Marie Jamison

Nadim Khlat

Marcus Granger-Jones

Ruediger Bauder

Joshua James Caron

Oliver Desmond Patterson

David W Kelly

Kelvin Kai Tuan Yan

Stephen Carl Kuehne

Jan Edward Vandemeer

Elizabeth C Glass

Jeppe Korshøj Bendixen

Daniel J Dolan, Jr

Milton Beachy

Mario Pita

Brian White

Don Willis

Thomas M Oberdick

Alan R Olds

Bradley Curtis Deselms

Dennis P Biondi

Jinhua Zhong

A multi-mode antenna tuner circuit and related apparatus are provided. The multi-mode antenna tuner circuit can be configured to operate in a low-current mode or a high-power mode. When operating in the high-power mode, the multi-mode antenna tuner circuit can provide full-fledged functionalities and consume a higher amount of current. In contrast, in the low-current mode, the multi-mode antenna tuner circuit provides reduced functionality and consumes a lower amount of current. In this regard, in a wireless communication apparatus employing multiple multi-mode antenna tuner circuits, it is possible to opportunistically configure some multi-mode antenna tuner circuits to operate in the low-current mode based on an operating environment (e.g., frequency band, location, etc.) and internal state (e.g., battery level, signal strength, etc.) of the wireless communication apparatus. As a result, it may be possible to reduce consumption and heat dissipation without compromising performance of the wireless communication apparatus.

Multi-mode antenna tuner circuit and related apparatus

Disclosed is radio frequency switch circuitry that includes a switch branch having a first branch terminal coupled to a first signal port and a second branch terminal coupled to a second signal port, and a branch control terminal, wherein the switch branch has both an on-state and an off-state to control passage of a radio frequency signal between the first signal port and the second signal port in response to a control signal applied to the control terminal. The radio frequency switch circuitry further includes an isolation inductor coupled between the first branch terminal and the second branch terminal such that the isolation inductor is in parallel with the switch branch, wherein the isolation inductor has a given inductance that provides resonance with a total off-state capacitance of the switch branch in the off-state at a center frequency of the radio frequency signal.

Radio frequency switch branch circuitry

A transistor-based radio frequency (RF) switch that provides symmetric RF impedance is disclosed. The transistor-based RF switch includes an N number of main field-effect transistors (FETs) stacked in series between a first end node and a second end node. A first end-network is coupled between the first end node and a proximal gate node. The first end-network provides a first variable impedance that equalizes a drain-to-source voltage of the first main FET to within a predetermined percentage of a drain-to-source voltage of a second main FET of the N number of main FETs. A second end-network is coupled between the second end node and the distal gate node, wherein the second end-network provides a second variable impedance to equalize the drain-to-source voltage of an Nth main FET to within the predetermined percentage of the drain-to-source voltage of an N&#x2212;1 main FET of the N number of main FETs.

Transistor-based radio frequency (RF) switch

A radio frequency switch system includes a plurality of radio frequency switch circuitries that each include a switch branch coupled between a first branch terminal and a second branch terminal and are configured to allow passage of a radio frequency signal through the switch branch in an on-state and to block the radio frequency signal from passing through the switch branch in an off-state in response to a control signal applied to a branch control terminal of the switch branch. Also included is a switch controller configured to apply the control signal to the branch control terminal of the switch branch of each of the plurality of radio frequency switch circuitries, wherein the control signal has a first voltage level that places the switch branch in the on-state and a second voltage level that places the switch branch in the off-state without digital signal decoding of the control signal.

Radio frequency switch system

An overvoltage detector for an RF switch is disclosed. The overvoltage detector is made up of circuitry having a detector output that couples to a controller, a body voltage input that couples to a charge pump, and a body voltage output that couples to a body terminal of the RF switch. The overvoltage detector is configured to detect an overvoltage across the RF switch by monitoring body leakage current flowing between the body voltage input and the body voltage output. Upon detecting body leakage current over a predetermined level, the overvoltage detector generates an overvoltage signal at the detector output to indicate an overvoltage across the RF switch.

Overvoltage detector for an RF switch

A first stacked RF switch, which operates in one of an ON mode and an OFF mode, and includes a group of RF switching circuits coupled in series between a first RF switch connection node and a second RF switch connection node, is disclosed. The group of RF switching circuits includes a first RF switching circuit, which includes a first switching transistor element coupled between a first source connection node and a first drain connection node, a first source/drain (S/D) bias resistive element coupled across the first switching transistor element, and a first S/D shorting circuit coupled across the first S/D bias resistive element. During the ON mode, the first switching transistor element is ON and the first S/D shorting circuit is ON. During a first interval immediately following a transition from the ON mode to the OFF mode, the first S/D shorting circuit is ON.

Stacked RF switch with fast switching speed

Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a source connected to the signal input terminal, a drain connected to the signal output terminal, a gate for controlling the on/off state of the switching device, and a body terminal. Each stage includes a gate resistor connected in series between the control input terminal and the gate and a rectification circuit for rectifying a voltage across the source and drain to provide a local bias voltage to the body terminal.

RF branch with improved power handling

Improved Radio Frequency (RF) switches are provided herein. According to one aspect, an RF switch comprises one or more stages. In one embodiment, each stage comprises a signal input terminal, a signal output terminal, a control input terminal, and a switching device having a first terminal connected to the signal input terminal, a second terminal connected to the signal output terminal, and a third terminal for controlling the on/off state of the switching device. Each stage includes a first resistor connected in series between the control input terminal and the third terminal, a first bypass switch for electrically bypassing the first resistor, and a second resistor connected in series between the signal input terminal and the signal output terminal. The first resistors form a first bias network, the second resistors form a second bias network, and the switching devices are connected in series.

RF branch with accelerated turn-on and high Q value

Radio frequency switch circuitry is disclosed having first and second port terminals, a switch branch having first and second branch terminals, and a branch control terminal, wherein the switch branch is configured to pass an RF signal between the first and second branch terminals in an on-state and block the RF signal from passing between the first and second branch terminals in an off-state in response to a control signal that is coupled with the RF signal and received at the first port terminal. Control signal decoupling circuitry has a control signal input terminal coupled to the first port terminal to receive the control signal coupled to the RF signal and a control signal output terminal coupled to the branch control terminal, wherein the control signal decoupling circuitry is configured to decouple the control signal from the RF signal and provide the control signal to the branch control terminal.

Radio frequency switch circuitry

Disclosed is a transistor-based switch having an N number of main field-effect transistors (FETs) stacked in series such that a first terminal of a first main FET of the N number of main FETs is coupled to a first end node and a second terminal of an Nth main FET of the N number of main FETs is coupled to a second end node, wherein N is a finite number greater than five. The transistor-based switch further includes a gate bias network having a plurality of gate resistors, wherein individual ones of the plurality of gate resistors are coupled to gate terminals of the N number of main FETs. A common gate resistor is coupled between a gate control input and a gate control node of the plurality of gate resistors, and a capacitor is coupled between the gate control node and a switch path node of the main FETs.

An RF switch having an M number of FETs that are stacked in series and coupled between a first end node and a second end node wherein each of the M number of FETs has a gate is disclosed. A resistive network is coupled between a common mode (CM) node and the gate for each of the M number of FETs such that a resistance between the CM node and each gate of the M number of FETs is substantially equal. Biasing circuitry coupled to the CM node is configured to sense a breakdown current flowing through the CM node, and in response to the breakdown current, generate a compensation signal that counters deviations of drain to source voltage across individual ones of the M number of FETs due to an applied RF voltage across the M number of FETs while the RF switch is in an OFF state.

RF switch having reduced signal distortion

A Radio Frequency (RF) switch having two or more stages coupled in series is disclosed. A first Field-Effect Transistor (FET) with a first control terminal is coupled across a gate resistor to shunt the gate resistor when the first FET is on. An RF switching device is configured to pass an RF signal between a signal input and a signal output when the RF switching device is on. A second FET having a second control terminal coupled to an acceleration output is configured to shunt the RF switching device when the second FET is on. A third FET is coupled between the first control terminal and the signal input for controlling charge on a gate of the first FET. A third control terminal of the third FET is coupled to an acceleration input for controlling an on/off state of the third FET.

Radio frequency (RF) switch with on and off switching acceleration

Antenna tuning circuitry includes an antenna tuning node, an antenna tuning switch, and a resonant tuning circuit. The antenna tuning node is coupled to a resonant conduction element of an antenna. The antenna tuning switch and the resonant tuning circuit are coupled in series between the antenna tuning switch and the antenna tuning node, such that the resonant tuning circuit is between the antenna tuning node and the antenna tuning switch. The resonant tuning circuit is configured to resonate at one or more harmonic frequencies generated by the antenna tuning switch such that a high impedance path is formed between the antenna tuning switch and the antenna tuning node at harmonic frequencies generated by the antenna tuning switch. Accordingly, harmonic interference generated by the antenna tuning switch is prevented from reaching the antenna, while simultaneously allowing for tuning of the antenna.

Antenna tuning circuitry with reduced interference

The present disclosure relates to a silicon-on-insulator (SOI) substrate structure with a buried dielectric layer for radio frequency (RF) complementary metal-oxide semiconductor (CMOS) switch fabrications. The buried dielectric layer suppresses back-gate transistors in the RF CMOS switches fabricated on the SOI substrate structure. The SOI substrate structure includes a silicon handle layer, a silicon oxide layer over the silicon handle layer, a buried dielectric layer over the silicon oxide layer, and a silicon epitaxy layer directly over the buried dielectric layer.

Suppression of back-gate transistors in RF CMOS switches built on an SOI substrate

Antenna tuning switch circuitry includes an input port, a shunt switch, control circuitry, and an integrated ground. The shunt switch is coupled between the input port and the integrated ground. The control circuitry includes a control signal input port, a switch driver output port coupled to the shunt switch, and a ground connection port coupled to the integrated ground. The shunt switches, the RF input ports, the control circuitry, and the integrated ground are monolithically integrated on a single semiconductor die. The antenna tuning switch circuitry is adapted to selectively couple the input port to the integrated ground in order to alter one or more operating parameters of an attached antenna. By monolithically integrating the shunt switch together with the control circuitry and the integrated ground, the ON state impedance and the parasitic OFF state impedance of the antenna tuning switch circuitry can be significantly improved.

Dedicated shunt switch with improved ground

Growing community of inventors

Oak Ridge, NC, United States of America

Daniel Charles Kerr