Stmicroelectronics S.a.

Daniel Caspar

Richard P Fournel

Cyrille Dray

Philippe Gendrier

Philippe Candelier

Sébastien Poirier

The semiconductor memory device includes an electrically erasable programmable non-volatile memory cell having a single layer of gate material and including a floating-gate transistor and a control gate. The source, drain and channel regions of the floating-gate transistor form the control gate. Moreover, the memory cell includes a dielectric zone lying between a first part of the layer of gate material and a first semiconductor active zone electrically isolated from a second active zone incorporating the control gate. This dielectric zone then forms a tunnel zone for transferring, during erasure of the cell, the charges stored in the floating gate to the first active zone.

Electrically erasable and programmable, non-volatile semiconductor memory device having a single layer of gate material, and corresponding memory plane

A non-volatile memory device includes a memory plane formed from a matrix of memory cells, each including an access transistor and a capacitor. The matrix includes first and second groups of cells laid out in a first and second directions. Each first group includes cells whose transistor gates are connected together by a first metallization, whose upper capacitor electrodes are connected together by a second metallization, and whose transistor sources are not connected together. Each second group includes cells whose transistor sources are connected together by a third metallization, whose transistor gates are not connected together, and whose upper capacitor electrodes are not connected together. The device includes control means capable of applying chosen voltages to the first, second, and third metallizations so as to selectively program a single one of the cells by damaging its dielectric without programming the other cells and without damaging the transistors of the cells.

Memory device that can be irreversibly programmed electrically

The FAMOS memory location comprises a single floating gate (GR) overlapping an active surface of a semiconductor substrate according to at least two asymmetrical overlap profiles (PF , PF ) so as to define at least two electrodes in the active region. Memory location programming means (MC, SW) are capable of selectively applying different predetermined sets of bias voltages to the electrodes so as to confer at least three programming logic levels on the memory location.

Memory cell of the famos type having several programming logic levels

A FAMOS memory cell is electrically erased. The FAMOS memory cell may be electrically erased by applying to the substrate a voltage having a value at least 4 volts higher than the lower of a voltage applied to the source and a voltage applied to the drain. The voltage applied to the substrate is also less than a predetermined limit above which the memory cell is destroyed.

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Saint Hilaire du Touvet, France

Daniel Caspar