Intel Corporation

Daniel Cartagena

Efraim Rotem

Krishnakanth Venkata Sistla

Nir Rosenzweig

Jorge Pedro Rodriguez

Dorit Shapira

Anand K Enamandram

Vivek Garg

Nikhil Gupta

Corey D Gough

An apparatus is provided, where the apparatus includes a plurality of components; a first sensing system to measure first power consumed by first one or more components of the plurality of components; a second sensing system to measure second power consumed by the apparatus; an analog-to-digital converter (ADC) to generate an identification (ID) that is representative of the second power consumed by the apparatus; and a controller to allocate power budget to one or more components of the plurality of components, based on the measurement of the first power and the ID.

Power management based on real time platform power sensing

A dynamic adjustment of core power can reduce thermal margin between thermal design power (TDP) and an allowable thermal load. For example, by focusing directly on the core temperatures explicitly, a per-core closed loop temperature controller (pCLTC) can remove conservatism induced by the power level 1 policy (PL1, a policy which defines frequency and/or power for the processor under sustained load) thereby allowing for increased processor performance when there exists margin in the thermal system.

Systems, methods and devices for using thermal margin of a core in a processor

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Chandler, AZ, United States of America

Daniel Cartagena