Transwitch Corporation

International Telephone and Telegraph Corporation

University of Connecticut

Opel, Inc.

Itt Corporation

International Standard Electric Corporation

Transwitch Corporaton

Daniel C Upp

Subhash Chandra Roy

Geoff W Taylor

Michael M Renault

Santanu Das

Jianhong Cai

Alan J Lawrence

William T Cochran

William Lipp

William G Bartholomay

Dan H Wolaver

Jitender K Vij

Rajen S Ramchandani

Frederick R Carter

Rohinton Dehmubed

John M Cotton

Ramon C Chea, Jr

Steven Benoit

Eugene L Parrella

David Toebes

Bidyut Parruck

Joseph R Yudichak

Jozef Cornu

Suvhasis Mukhopadhyay

Jean R Taeymans

Robert W Hamlin, Jr

Kumar Shakti Singh

Jeffrey N Denenberg

Sachin Mathur

Chitra Wadhwa

Francoise C Van Simaeys

Pawan Goyal

Mikio S Ichiba

Murray Rubinstein

Michael L Kuras

Johan M Danneels

Herbert J Toegel

Vikas Kumar

Anna M Leurs

Arnab Basak

Bart Brosens

Alberto Bricca

Kris Van Aken

William B Lipp

Ramses Valvekens

Interference caused by the propagation of a transmit signal transmitted from a transmit antenna to a receive antenna is effectively cancelled by an improved signal cancellation system. The system includes an interference cancellation signal generator that generates a time-delayed and amplitude-reduced representation of said transmit signal. A summing stage is operably coupled to the interference cancellation signal generator and the receive antenna. The summing stage subtracts the time-delayed and amplitude-reduced representation of the transmit signal from a receive signal to substantially cancel the interference. The interference cancellation signal generator preferably includes a novel programmable optical delay line that introduces a variable amount of optical delay to an optical signal derived from said transmit signal in addition to a thyristor-based sigma delta modulator that converts samples of the transmit signal to into a digital signal in the optical domain.

Integrated circuit for programmable optical delay

Methods for retiming SONET signals include demultiplexing STS-1 signals from an STS-N signal, buffering each of the STS-1 signals in a FIFO, determining the FIFO depth over time, and determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. According to the presently preferred embodiment, each FIFO is 29 bytes deep. If FIFO depth is 12-17 bytes, no leaking is performed. If the depth is 8-12 bytes or 17-21 bytes, a slow leak rate is set. If the depth is 4-8 bytes or 21-25 bytes, a fast leak rate is set. If the depth is 0-4 bytes or 25-29 bytes, pointer movements are immediate. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received during a sliding window of n&#xd7;32 seconds (n&#xd7;256,000 frames).

SONET/SDH SPE/virtual container retiming with adaptive dual pointer leak rate computation

An optoelectronic pulse generator is provided that includes a thyristor detector/emitter device having an input port and an output port. The thyristor detector/emitter device is adapted to detect an input optical pulse supplied to the input port and to produce an output optical pulse (via laser emission) and an output electrical pulse in response to the detected input optical pulse. The output optical pulse is output via the output port. An optical feedback path is operably coupled between the output port and the input port of the thyristor detector/emitter device. The optical feedback path supplies a portion of the output optical pulse produced by the thyristor detector/emitter device to the input port, thereby causing the thyristor detector/emitter device to produce a sequence of output optical pulses and a corresponding sequence of output electrical pulses. Preferably, the optical feedback path comprises a programmable optical delay line realized by a network of in-plane waveguide structures and directional coupler devices that are integrally formed with the thyristor device structure of the detector/emitter device.

Optoelectronic clock generator producing high frequency optoelectronic pulse trains with variable frequency and variable duty cycle and low jitter

Photonic sigma delta analog-to-digital conversation employing dual heterojunction thyristors

An optoelectronic integrated circuit includes a resonant cavity formed on a substrate. A heterojunction thyristor device is formed in the resonant cavity and operates to detect an input optical pulse (or input electrical pulse) and produce an output optical pulse via laser emission in response to the detected input pulse. The heterojunction thyristor device includes a channel region that is coupled to a current source that draws current from the channel region. Time delay between the input pulse and output optical pulse may be varied by configuring the current source to draw constant current from the channel region and modulating the intensity of the input pulse, or by varying the amount of current drawn from the channel region by the current source. The heterojunction thyristor device may be formed from a multilayer structure of group III-V materials, or from a multilayer structure of strained silicon materials. A plurality of such heterojunction thyristor based optoelectronic integrated circuits can be used to provide variable pulse delay over a plurality of channels. In addition, the heterojunction thyristor device is easily integrated with other optoelectronic devices formed from the same growth structure to form monolithic optoelectronic integrated circuits suitable for many diverse applications, including phased array communication systems.

Optoelectronic device employing at least one semiconductor heterojunction thyristor for producing variable electrical/optical delay

A network switch includes at least one port processor and at least one switch element. The port processor has an SONET OC-x interface (for TDM traffic), a UTOPIA interface (for ATM and packet traffic), and an interface to the switch element. In one embodiment, the port processor has a total I/O bandwidth equivalent to an OC-48, and the switch element has 12&times;12 ports for a total bandwidth of 30 Gbps. A typical switch includes multiple port processors and switch elements. A data frame of 9 rows by 1700 slots is used to transport ATM, TDM, and Packet data from a port processor through one or more switch elements to the same or another port processor. Each frame is transmitted in 125 microseconds; each row in 13.89 microseconds. Each slot includes a 4-bit tag plus a 4-byte payload. The slot bandwidth is 2.592 Mbps which is large enough to carry an E-1 signal with overhead. The 4-bit tag is a cross connect pointer which is setup when a TDM connection is provisioned. The last twenty slots of the frame are reserved for link overhead. Thus, the frame is capable of carrying the equivalent of 1,680 E-1 TDM signals. For ATM and packet data, a PDU (protocol data unit) of 16 slots is defined for a 64-byte payload. The PDUs are self-routed through the switch with a 28-bit routing tag which allows routing through seven switch stages using 4-bits per stage. Bandwidth is arbitrated among ATM and Packet connections while maintaining TDM timing.

Network switch which supports TDM, ATM, and variable length packet traffic and includes automatic fault/congestion correction

Method for switching ATM, TDM, and packet data through a single communications switch

Method of multicasting data through a communications switch

Method and apparatus for switching ATM, TDM, and packet data through a single communications switch while maintaining TDM timing

Methods for retiming and realigning SONET signals include demultiplexing STS-1 signals from an STS-3 signal, buffering each of the three signals in a FIFO, determining the FIFO depth over time, determining a pointer leak rate based in part on FIFO depth and also based on the rate of received pointer movements. For a 28-byte deep FIFO, if the depth of a FIFO is 12-16 bytes, no pointer leaking is performed. If the depth is 0-4 bytes, an immediate positive leak is performed. If the depth is 24-28, an immediate negative leak is performed. If the depth is 5-11 bytes a calculated positive leak is performed. If the depth is 17-23 bytes, a calculated negative leak is performed. The calculated leak rates are based on the net number of pointer movements (magnitude of positive and negative movements summed) received every 32 seconds (256,000 frames).

Methods and apparatus for retiming and realigning sonet signals

The desynchronizer of the present invention includes two FIFOs. The first FIFO has two address counters (write and read), an intermediate count register, circuitry for calculating the difference between the write and intermediate counts and the intermediate and read counts, a logic block for performing pointer leak and other arithmetic functions, and a digitally controlled oscillator (DCO). The second FIFO has read and write counters, a phase-frequency detector, and an internal VCO controlled by length measurements of the second FIFO. The desynchronizer receives data bits, pointer movement indications, and stuff indications from a DS-3/E3 demapper and, using the first FIFO, the address counters, etc., removes the low frequency components, including SONET/SDH systemic gapping in order to provide the second FIFO with a DS-3/E3 signal having a high frequency phase modulation. The second FIFO removes the remaining high frequency gapping jitter.

Method and apparatus for desynchronizing a DS-3 signal and/or an E3 signal from the data portion of an STS-STM payload

The apparatus includes a separate line side inlet queue for each GFR VC, a single network side outlet queue for all GFR VCs, a single network side inlet queue for all GFR VCs, a single line side outlet bulk processing queue with a post queue packet processor followed by separate line side outlet queues for each line, a network side outlet queue monitor, and a line side inlet queue controller. The network side outlet queue monitor is coupled to the line side inlet queue controller so that the network side outlet queue monitor can send messages to the line side inlet queue controller. According to one of the methods of the invention, the network side outlet queue monitor sends messages to the line side inlet queue controller directing the line side inlet queue controller to send data from the line side GFR queues based on the status of the network side outlet GFR queue. According to another method of the invention, the line to side inlet queue controller discards packets for a GFR VC if congestion is indicated. According to still another method of the invention, the post queue packet processor discards packets above the PCR if the size of the line side outlet bulk processing queue exceeds a threshold size and discards packets above the MCR if discarding packets above the PCR fails to sufficiently reduce the size of the line side outlet bulk processing queue.

Methods and apparatus for managing traffic in an atm network

An asynchronous data transfer and source traffic control system includes a bus master and a plurality of bus users coupled to a bidirectional data bus. The bus master provides two clock signals to each bus user, a system clock and a frame clock. The frame clock designates the start of a frame. A frame format preferably includes fifteen or sixteen system clock cycles, the first of which is designated the request field and the last of which includes a grant field. One or more other cycles may be assigned control and/or routing information and the remainder of the cycles comprise a data field of fixed length. During the request field, any number of bus users may request access which is received by the bus master. During the grant field, the bus master grants access to a selected bus user for the entire data portion of the next frame. Which user is granted access to the next frame is determined according to an arbitration algorithm in the bus master which may be unknown to the bus users. The asynchronous data transfer and source traffic control system has particular application in accommodating the transfer of the contents of ATM cells used in BISDN systems.

Asynchronous data transfer and source traffic control system

An SRTS clock recovery apparatus and method are provided. The apparatus broadly includes a controllable destination node clock generator such as a digitally controllable oscillator, a block for generating a local RTS-related value from the destination node clock and the system reference clock, and a comparator which compares the incoming RTS-related value to the local RTS related value to provide a feedback error or control signal which is used to adjust the controllable clock generator. If desired, a filter which filters the error signal can be provided in the loop. With the feedback loop as provided, when the destination node clock is faster than the source clock, the error signal will cause the destination node clock to slow, and vice versa.

Closed loop clock recovery for synchronous residual time stamp

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Southbury, CT, United States of America

Daniel C Upp