Codex Corporation

Daniel C Scavezze

Alexander Herman

Gerald A Kammerer

Murray H Bolt

Miriam E Leeser

William R Prescott

A large number (e.g., 20 or more) independent processors are connected by a network that provides high data throughput (e.g., 64 megabits/second). The network has redundant data, arbitration, and status/control buses. The buses extend across a plurality of microstripline backplanes connected together by impedance-matched twisted-pair cables. Data is transmitted in packets, along with status signals that provide error detection information.

Interconnection network for multiple processors

A data communication network over which data handling devices can transmit and receive packets among themselves having a bus, a number of subnetworks (each having interfaces for connecting a number of devices to each subnetwork), a concentrator for connecting each interface to the bus, each concentrator having a transceiver for transmitting, to the bus and to devices connected to each subnetwork, packets originating from devices within a subnetwork (transmitted packets), and for receiving from the bus packets originating from other subnetworks (received packets), collision avoidance circuitry for monitoring transmission attempts by devices connected to the subnetwork, for detecting competing transmission attempts that would create a collision on the subnetwork, and, upon such detection, permitting a selected attempt to enter the subnetwork, while preventing other attempts from entering it, collision detection circuitry for monitoring the bus and preventing all attempted transmissions from entering the bus whenever a packet from another subnetwork is present on the bus. In another aspect the interface means and the concentrator means include a network interface unit and a further interface unit.

Growing community of inventors

Chelmsford, MA, United States of America

Daniel C Scavezze