Ncr Corporation

Mitsubishi Semiconductor America, Inc.

Daniel C Robbins

Edward A McDonald

Thomas F Heil

Gene F Young

Arthur F Cochcroft, Jr

Jimmy D Pike

Craig A Walrath

P Chris Raeuber

A computer,has an input device,keyboard with two sets of input keys,separated by a touch pad,The touch pad,is accessed by an operator's index finger from the home row of keys, typically the next to last row.

Single finger controlled computer input apparatus and method

A device driver initiates a DMA transfer and repeatedly reads a semaphore from a specified location in system memory. Upon completion of a DMA transfer, a DMA controller writes a semaphore containing status information to the specified location in system memory, informing the device driver that the DMA transfer is completed. A cache memory for the specified location in system memory is provided to further reduce the latency between DMA transfers.

DMA controller with semaphore communication protocol

A convertible computer includes a base portion having an operative side and a rear side. The computer further includes a display portion, pivotally attached to the base portion, having an operative side and a rear side, the rear side of the display portion being positionable substantially adjacent the rear side of the base portion. Moreover, the computer includes a cover positionable over the operative side of the base portion.

Computer configuration which allows conversion between multiple

Multiple processor systems are configured to include at least two system or memory buses with at least two processors coupled to each of the system buses, and at least two I/O buses which are coupled to the system buses to provide multiple expansion slots hosting up to a corresponding number of I/O bus agents for the systems at the cost of a single system bus load for each I/O bus. Each of the system and I/O buses are independently arbitrated to define decoupled bus systems for the multiple processor systems of the present invention. Main memory for the systems is made up of at least two memory interleaves, each of which can be simultaneously accessed through the system buses. Each of the I/O buses are interfaced to the system buses by an I/O interface circuit which buffers data written to and read from the main memory or memory interleaves by I/O bus agents.

Architectures for computer systems having multiple processors, multiple

A buffer management scheme for optimally configuring a data buffer within a computer system which includes a plurality of bus masters connected through a Micro Channel bus and the data buffer to a shared resource, such as memory. The scheme decodes unique four-bit Micro Channel arbitration values assigned to the bus masters to retrieve buffer configuration parameters stored within a register file containing different configuration parameters for each bus master. The data buffer is dynamically configured for optimal performance with each bus master having control of the Micro Channel bus in accordance with the parameter data retrieved from the register file.

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Easley, SC, United States of America

Daniel C Robbins