Nxp Usa, Inc.

Mtekvision Co., Ltd.

Daniel C Laroche

Ali Osman Ors

Malcolm D Stewart

Michael J Rochford

Rabindra Guha

Craig Robert Moulder

Trevor Graydon Burton

Xiaoyin Xu

Jean-François Deschênes

An asymmetrical processing system is provided. The processor has a vector unit comprised of one or more computational units coupled with a vector memory space and a scalar unit coupled with a data memory space and the vector memory space, the scalar unit accessing one or more memory locations within the vector memory space.

Asymmetrical processor memory architecture

A method, system, and apparatus are provided for managing multiple DMA channels in different DMA modes by processing command sequences associated with different virtual DMA channels and stored in a command queue structure, such that a first command sequence is processed to directly configure one or more first register descriptors at a context store to implement a direct configuration DMA mode for a first virtual channel, a second command sequence is processed to initiate a fetch of a linked list descriptor chain for loading one or more second register descriptors at a second DMA channel context store register to implement a link list configuration DMA mode for a second virtual channel, and a third command sequence is processed to retrieve an instruction program for loading into the command queue structure and execution by the DMA controller to implement a program configuration DMA mode for a third virtual channel.

Multi-channel DMA system with command queue structure supporting three DMA modes

A system and method of mapping of a processing task to a target processor is provided. Kernels associated with unit of processing defined for a processor to operate on a processing operation on the target processor required to performing the processing task. A directed acyclic graph (DAG) comprising the kernels and specifying connections between the one or more kernels represents the desired processing task to be executed by the target processor is resolved from the kernels defined in the DAG to a process executed by a processor architecture of the target processor. Data sequencing is determined from the DAG for memory usage in executing the process. Host code is generated to configure and execute the process in relation to the kernel execution for the process resolved for the processing task.

Heterogenous multicore processor configuration framework

A method and device for memory access in processors is provided. A processor, comprising a plurality of computational units, is capable of executing a single instruction on multiple pieces of data simultaneously (SIMD). A read operation is initiated to load data from memory into the plurality of computational units (CUs) arranged into a plurality of CU groups. The memory is arranged into a plurality of memory macro-blocks each associated with a respective CU group of the plurality of CU groups. For each CU group a respective first memory address is determined and for each CU group, the data in the associated memory macro-block is accessed at the respective first memory address.

Memory access for a vector processor

A reconfigurable vector processor is described that allows the size of its vector units to be changed in order to process vectors of different sizes. The reconfigurable vector processor comprises a plurality of processor units. Each of the processor units comprises a control unit for decoding instructions and generating control signals, a scalar unit for processing instructions on scalar data, and a vector unit for processing instructions on vector data under control of control signals. The reconfigurable vector processor architecture also comprises a vector control selector for selectively providing control signals generated by one processor unit of the plurality of processor units to the vector unit of a different processor unit of the plurality of processor units.

Apparatus and method of vector unit sharing

The invention proposes a simple method for controlling distributed functional units (FU) in a system. It offloads the main system processor from intermediate status monitoring. The sequencer controlled system comprises a plurality of functional units, a processor operatively coupled to the plurality of functional units through a bus, a sequencer having a set of registers, and an interrupt source register configured for interrupt polling. The registers are configured to control the timing of at least one operation of the functional units with stored instructions for each of the functional units. The processor sets up at least some of the registers through the bus for the initial configuration and the sequencer is activated by the processor.

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Kemptville, Canada

Daniel C Laroche