Mostek Corporation

Thomson Components-mostek Corporation

Daniel C Guterman

Donald R Dias

Robert J Proebsting

Ching-Lin Jiang

Horst Leuschner

James D Kupec

A simple, compact voltage reference circuit for an NMOS integrated circuit comprises a series connected depletion transistor with its gate at ground and an enhancement transistor with its gate connected to an output node between the two transistors.

Simple NMOS voltage reference circuit

A nonvolatile memory cell (16) is fabricated on a substrate (12) and includes a source region (46) and drain regions (48, 50 and 52). Step oxides (40, 42 and 44) are fabricated respectively over the regions (46, 48 and 52). A gate oxide (58) is formed between the step oxides (40 and 42). A thin oxide tunneling element (74) is fabricated between the step oxides (42, 44) and over the drain region (50). A floating gate (38) comprising a polysilicon layer is fabricated over the step oxides (40, 42, 44), the gate oxide (58) and the tunneling element (74). An insulation layer (36) is fabricated over the floating gate (38). Finally, a control gate (34) is fabricated over the insulating layer (36) to provide capacitive coupling to the floating gate (38). The nonvolatile memory cell (16) has enhanced capacitive coupling between the control gate (34) and the floating gate (38) while it has a minimum of capacitive coupling between the floating gate (38) and the source and drain regions (46, 48, 50, 52) in the substrate (12).

Nonvolatile MOS memory cell with tunneling element

A compact memory cell combines a volatile dynamic storage section with a shadow nonvolatile section in two vertically stacked element arrays.

Dynamic RAM with nonvolatile shadow memory

An electrically erasable programmable read only memory employs a single unsteered on-chip high voltage generator that applies high voltage simultaneously to all cells on the chip.

E.sup.2 PROM having bulk storage

A nonvolatile random access memory cell (10) includes a static random access memory circuit and a corresponding nonvolatile memory circuit. The volatile memory circuit operates in a conventional manner and has first and second data states. Upon receipt of a store command signal a charge storage node is driven to either a first or a second charge state, depending upon the data state in the volatile memory circuit. For one charge state the charge storage signal is gated through a transistor (64) and a capacitor (68) to a floating gate node (44). Charge is transferred to and from the floating gate node (44) through current tunneling elements (48,50) which comprise a dielectric fabricated on a monocrystalline substrate. For the recall operation a recall command signal is applied to a transistor (52) which couples a transistor (42) to the DATA node (22) of the volatile memory circuit. If a positive charge state has been stored at the charge storage node (44) the transistor (42) is rendered conductive to pull the DATA node (22) to ground to restore the data state to the volatile memory circuit. If a negative charge state has been stored at the charge storage node (44) there is no load applied to either the DATA node (20) or the DATA node (22). The cross-couple transistors, (12,14) are fabricated to have different lengths such that the node (22) is driven to a high voltage state whenever a default condition is encountered, thereby restoring the original data state to the volatile memory circuit.

MOS Random access memory cell with nonvolatile storage

A user-programmable and reprogrammable programmed logic array includes a self-indexing pointer to direct successive input signals to the proper cell within the array. A particular application is that of a ROM patch to correct coding errors in a ROM.

User reprogrammable programmed logic array

A nonvolatile static random access memory cell (10) for storing data in a nonvolative state and recalling the data in its true state is disclosed. Cross-coupled transistors (12, 14) are provided having respective first and second nodes (16, 18) which are maintained at complementary logic states for volatile data storage. At least one tunnel capacitor (34), each having a floating node (36) is operatively coupled to the gate and drain terminals of one of said cross-coupled transistors (12, 14). At least one switch transistor (48) is operatively coupled to one of the first and second nodes (16, 18) and to one tunnel capacitor floating node (36). The at least one tunnel capacitor (34) and the at least one switch transistor (48) operatively coact for nonvolatile saving of volatile data stored in the cross-coupled transistors (12, 14), for recalling nonvolatile stored data in its true state to the cross-coupled transistors (12, 14), by the capacitive imbalance on the first and second nodes (16, 18). Coupling means (50, 54) operatively connected between the switch transistors (48, 52) and the first and second nodes (16, 18) are coupled to one supply (V.sub.cc or V.sub.SS) in such fashion as to prevent interference between volatile and nonvolative data storage.

Growing community of inventors

Plano, TX, United States of America

Daniel C Guterman