International Business Machines Corporation

Adeia Semiconductor Bonding Technologies Inc.

Globalfoundries Inc.

Other

Advanced Micro Devices Corporation

Cornell Research Foundation Inc.

Globalfoundries U.S. 2 LLC

Toshiba America Electronic Components, Inc.

Applied Materials, Inc.

Freescale Semiconductor,inc.

Tessera LLC

Clark Instrumentation, Inc.

Daniel C Edelstein

Chih-Chao Yang

Takeshi Nogami

Anthony K Stamper

Satyanarayana Venkata Nitta

Son Van Nguyen

Cyprian Emeka Uzoh

Elbert Emin Huang

Hosadurga K Shobha

Alfred Grill

Theodorus E Standaert

Timothy Joseph Dalton

Stephen McConnell Gates

Andrew Herbert Simon

Jeffrey P Gambino

Shom Ponoth

Cyril Cabral, Jr

Eugene John O'Sullivan

Vincent James McGahay

Robert Dennis Miller

Arne Watson Ballantine

John Anthony Fitzsimmons

Sampath Purushothaman

Matthew Earl Colburn

Thomas M Shaw

Terry Allen Spooner

Douglas Duane Coolbaugh

Kevin Shawn Petrarca

George Frederick Walker

David Lee Rath

Griselda Bonilla

Ashim Dutta

David V Horak

Tak H Ning

Haining S Yang

Michael Rizzolo

Hariklia Deligianni

Baozhen Li

Christopher Vincent Jahnes

Richard Paul Volant

Deborah A Neumayer

Zhong-Xiang He

Donald Francis Canaperi

Richard Anthony Conti

Juntao Li

Bahman Hekmatshoartabari

Keith Kwong Hon Wong

Kenneth Parker Rodbell

Qinghuang Lin

Wai-Kin Li

Robert Mark Rassel

John Michael Cotte

Anthony J Annunziata

Ramachandran Muralidhar

Jon Alfred Casey

Bruce Bennett Doris

Steven H Voldman

Timothy Harrison Daubenspeck

Kerry Bernstein

Sandra Guy Malhotra

Roy Rongqing Yu

Dirk Pfeiffer

Ronald G Filippi

Wilbur David Pricer

Thomas W Dyer

Christos Dimitrios Dimitrakopoulos

Vamsi Krishna Paruchuri

Daniel Sanders

Stephen Mark Rossnagel

Junjing Bao

Muthumanickam Sankarapandian

Chandrasekhar Narayan

Willi Volksen

Ruilong Xie

Lawrence Alfred Clevenger

Jack Allan Mandelman

Louis L Hsu

Rajiv V Joshi

Guy M Cohen

Mukta G Farooq

Ping-Chuan Wang

Michael A Gaynes

Timothy Dooling Sullivan

Oscar Van Der Straten

Paul Stephen Andry

Bucknell Chapman Webb

Sanjay C Mehta

Sri Muthuthamby Sri-Jayantha

Edmund Juris Sprogis

Yann Mignot

Ravikumar Ramachandran

Louis Lu-Chen Hsu

Gareth Geoffrey Hougham

Xiao Hu Liu

Yunpeng Yin

Yun-Yu Wang

Steven John Koester

Kailash Gopalakrishnan

Robert L Wisnieff

Sarunya Bangsaruntip

A semiconductor device and formation thereof. The semiconductor device includes a memory device located on top of a first bottom interconnect, wherein the first bottom interconnect is embedded in a first dielectric layer. The semiconductor device further includes a second bottom interconnect embedded in the first dielectric layer, wherein the second bottom interconnect is adjacent to the first bottom interconnect. A top surface of the second bottom interconnect is recessed relative to a top surface of the first bottom interconnect.

Recessed local interconnect semiconductor memory device

Interconnect structures containing metal oxide embedded diffusion barriers and methods of forming the same. Interconnect structures may include an Mlevel including an Mmetal in an Mdielectric, an Mlevel above the Mlevel including an Mmetal in an Mdielectric, an embedded diffusion barrier adjacent to the Mdielectric; and a seed alloy region adjacent to the Mmetal separating the Mmetal from the Mmetal. The embedded diffusion barrier may include a barrier-forming material such as manganese, aluminum, titanium, or some combination thereof. The seed alloy region may include a seed material such as cobalt, ruthenium, or some combination thereof.

Self-forming embedded diffusion barriers

A semiconductor structure includes a front-end-of-line level including a plurality of field effect transistors electrically connected to a back-end-of-line interconnect level. The back-end-of-line interconnect level is located on a first side of the front-end-of-line level. A backside power rail is embedded within a backside interlayer dielectric located on a second side of the front-end-of-line level opposing the first side of the front-end-of-line level. The backside power rail is electrically connected to at least one field effect transistor of the plurality of field effect transistors. At least one backside field effect transistor is formed on a first semiconductor layer disposed, at least in part, above a passive device region. A first side of the passive device region is in contact with the first semiconductor layer and a second side of the passive device region, opposing the first side, is in contact with the back-end-of-line interconnect level.

Semiconductor backside transistor integration with backside power delivery network

A novel bevel etch sequence for embedded metal contamination removal from BEOL wafers is provided. In one aspect, a method of processing a wafer includes: performing a bevel dry etch to break up layers of contaminants with embedded metals which, post back-end-of line metallization, are deposited on a bevel of the wafer, which forms a damaged layer on surfaces of the wafer, and then performing a sequence of wet etches, following the bevel dry etch, to render the bevel of the wafer substantially free of contaminants, wherein the sequence of wet etches includes etching the damaged layer to undercut and lift-off any remaining contaminants. A wafer, processed in this manner, having a bevel that is substantially free of contaminants is also provided.

Embedded metal contamination removal from BEOL wafers

A semiconductor device includes a bottom electrode contact disposed over one or more of a plurality of conductive lines, magnetoresistive random access memory (MRAM) pillars constructed over the bottom electrode contact, an encapsulation layer section disposed between a pair of the MRAM pillars such that an aspect ratio of a tight pitch gap between the pair of the MRAM pillars is reduced, and a dielectric disposed within the encapsulation layer section, wherein the dielectric fills an entirety of a space defined within the encapsulation layer section. The MRAM pillars have a generally rectangular-shaped or cone-shaped configuration and the encapsulation layer section has a generally U-shaped or V-shaped configuration.

Dielectric fill for tight pitch MRAM pillar array

A semiconductor structure forms two or more tightly pitched memory devices using a dielectric material for a gap fill material. The approach includes providing two adjacent bottom electrodes in a layer of an insulating material and above a metal layer. Two adjacent pillars are each above one of the two adjacent bottom electrodes where each pillar of the two adjacent pillars is composed of a stack of materials for a memory device. A spacer is around the vertical sides each of the two adjacent pillars. The dielectric material is on the spacer around the vertical sides each of the two adjacent pillars, on the layer of the insulating material between the two adjacent bottom electrodes. The dielectric material fills at least a first portion of a gap between the two adjacent pillars. A low k material covers the dielectric material and exposed portions of the layer of the insulating material.

High-density memory devices using oxide gap fill

A device relates to a semiconductor device. The semiconductor device includes a narrow-line bamboo microstructure integrated within a metal layer of the semiconductor device and a narrow-line polycrystalline microstructure. The narrow-line polycrystalline microstructure is integrated within the same metal layer as the narrow-line bamboo microstructure.

Advanced copper interconnects with hybrid microstructure

Low capacitance and high reliability interconnect structures and methods of manufacture are disclosed. The method includes forming a copper based interconnect structure in an opening of a dielectric material. The method further includes forming a capping layer on the copper based interconnect structure. The method further includes oxidizing the capping layer and any residual material formed on a surface of the dielectric material. The method further includes forming a barrier layer on the capping layer by outdiffusing a material from the copper based interconnect structure to a surface of the capping layer. The method further includes removing the residual material, while the barrier layer on the surface of the capping layer protects the capping layer.

Method of forming copper interconnect structure with manganese barrier layer

An electrode structure with an alloy interface is provided. In one aspect, a method of forming a contact structure includes: patterning a via in a first dielectric layer; depositing a barrier layer onto the first dielectric layer, lining the via; depositing and polishing a first metal layer (Element A) into the via to form a contact in the via; depositing a second metal layer (Element B) onto the contact in the via; annealing the first and second metal layers under conditions sufficient to form an alloy AB; depositing a third metal layer onto the second metal layer; patterning the second and third metal layers into a pedestal stack over the contact to form an electrode over the contact, wherein the alloy AB is present at an interface of the electrode and the contact; and depositing a second dielectric that surrounds the pedestal stack. A contact structure is also provided.

Electrode with alloy interface

A semiconductor device structure includes a metallization stack that has one or more patterned metal layers in a logic area and a memory area. At least one memory device is disposed above the metallization stack. A first level logic metal layer is coupled to a patterned metal layer of the one or more patterned metal layers in the logic area. A first level memory metal layer is formed above the first level logic metal layer and is coupled to a top electrode of the memory device stack. A distance between the one or more patterned metal layers in the logic area and the first level logic metal layer is smaller than the distance between the one or more patterned metal layers in the memory area and the first level memory metal layer.

Embedding magneto-resistive random-access memory devices between metal levels

A via structure and methods for forming a via structure generally includes a via opening in a dielectric layer. A conformal barrier layer is in the via opening; and a conductive metal on the barrier layer in the via opening. The conductive metal includes a recessed top surface. A conductive planarization stop layer is on the recessed top surface and extends about a shoulder portion formed in the dielectric layer, wherein the shoulder portion extends about a perimeter of the via opening. A fill material including an insulator material or a conductor material is on the conductive planarization stop layer within the recessed top surface, wherein the conductive planarization stop layer on the shoulder portion is coplanar to the insulator material or the conductor material. Also described are methods of fabricating the via structure.

Electrode-via structure

Copper interconnect structure with manganese barrier layer

A structure and a method for fabricating a bottom electrode for an integrated circuit device are described. A first dielectric layer is provided over a substrate and the first dielectric layer has a recess. A bottom electrode is formed over the recess. The bottom electrode consists of a microstud layer disposed completely within the recess of the dielectric and conforming to the recess, a bottom pedestal disposed on a top surface of the microstud and a top pedestal on a top surface of the bottom pedestal. The material used for the bottom pedestal has a lower electrochemical voltage than a material used for the microstud. A conductive element of the integrated circuit device is formed on a top surface of the bottom electrode. A first portion of the bottom electrode is disposed in and conforms to the recess. A second portion of the bottom electrode and the conductive element are conical sections.

Bottom electrode for semiconductor memory device

Compositions of matter, compounds, articles of manufacture and processes to reduce or substantially eliminate EM and/or stress migration, and/or TDDB in copper interconnects in microelectronic devices and circuits, especially a metal liner around copper interconnects comprise an ultra thin layer or layers of Mn alloys containing at least one of W and/or Co on the metal liner. This novel alloy provides EM and/or stress migration resistance, and/or TDDB resistance in these copper interconnects, comparable to thicker layers of other alloys found in substantially larger circuits and allows the miniaturization of the circuit without having to use thicker EM and/or TDDB resistant alloys previously used thereby enhancing the miniaturization, i.e., these novel alloy layers can be miniaturized along with the circuit and provide substantially the same EM and/or TDDB resistance as thicker layers of different alloy materials previously used that lose some of their EM and/or TDDB resistance when used as thinner layers.

Ultrathin multilayer metal alloy liner for nano Cu interconnects

Growing community of inventors

White Plains, NY, United States of America

Daniel C Edelstein