Analog Devices,inc.

Daniel Boyko

James M Wilson

Stuart Patterson

Colm J Prendergast

Olafur Mar Josefsson

Srivatsan Parthasarathy

Benoit Dufort

Piotr Olejarz

Ara Arakelian

Sirui Luo

Georges El Bacha

James F Potts

Chih Chuan Che

Lew Lahr

Matthew Aaron Hazel

Electrostatic discharge protection for high speed transceiver interface is disclosed. In one aspect, an electrical overstress (EOS) protection device includes an anode terminal and a cathode terminal, a silicon controlled rectifier, a second NPN bipolar transistor including a base connected to the anode terminal and an emitter connected to an emitter of the first PNP bipolar transistor, and a second PNP bipolar transistor including an emitter connected to an emitter of the second NPN bipolar transistor and a base connected to a base of the first PNP bipolar transistor. Two or more paths for current conduction are present during a positive overstress transient that increases a voltage of the anode terminal relative to the cathode terminal, including a first path through the silicon controlled rectifier and a second path through the second NPN bipolar transistor and the second PNP bipolar transistor.

Electrostatic discharge protection for high speed transceiver interface

Determining if a hermetically sealed MEMs device loses hermeticity during operation. In one embodiment, the MEMs device is an accelerometer. A test signal having an associated frequency above an operational frequency range for the accelerometer is provided to the accelerometer at an input during operation of the accelerometer for sensing an acceleration. The output signal of the accelerometer is filtered at least above the operational frequency range of the accelerometer producing a test output signal. The test output signal is then compared to a predetermined threshold to determine if the amplitude of the test output signal differs from the threshold. If the amplitude of the test output signal differs from the predetermined threshold, an error signal is produced indicating that hermeticity of the accelerometer has been lost.

System and method for run-time hermeticity detection of a capped MEMS device

A differential current output driver and a method for overvoltage protection of a differential current output driver circuit are provided. The output driver includes a differential current output driver circuit operable by a power supply voltage and including first and second driver transistors in a differential current configuration and first and second output pads, and an overvoltage protection circuit configured to generate a protected voltage in response to a voltage on at least one of the first and second output pads and an absence of the power supply voltage, and to apply the protected voltage to at least one transistor of the differential current output driver circuit.

Differential current output driver with overvoltage protection

An output driver in an integrated circuit includes a driver circuit operable by a power supply voltage and coupled to an output pad, and a driver power conditioner configured to generate a fractional pad voltage in response to a voltage on the output pad and to provide the fractional pad voltage to at least one transistor of the driver circuit as a protected supply voltage in response to an absence of the power supply voltage.

Output driver with overvoltage protection

A multistage dual logic level voltage translator for translating both high and low input logic levels to higher levels, at least one of which levels is above the maximum recommended voltage of transistors implementing the stages, includes an input stage for receiving input logic levels and an output stage including a high voltage converter having at least a pair of cross-coupled converter transistors responsive to the input stage and including a pair of clamping circuit connected one across each of the converter transistors, for providing the shifted low and high output logic levels.

Multistage dual logic level voltage translator

A calibration system for a communication system is provided featuring a transmitter circuit, a receiver circuit, a transmission medium having a transfer function for transmitting a signal between the transmitter and receiver circuits, and a calibration system responsive to the altered reference signal of the transmitter circuit for adjusting the reference signal level of one of the transmitter and receiver circuits to compensate for variations in the transmission signal due to the transfer function.

Calibration system for a communications system

A data processing chip with a flexible timing system and method for supplying clocks to a digital data processing system useful for power conservation. A phase locked loop generates a master clock from which a core clock and a system clock are derived. The frequency of each of the core and system clocks is independently controllable relative to the master clock and can be changed on the fly with glitch free and jitter free operation. The data processing chip is well suited for use in hand held electronic devices where power management is a concern. Power can be saved by lowering the frequency of the core clock, even for short intervals of time.

Microprocessor with power saving clock

An isolation system with analog communication across an isolation barrier includes an isolation barrier circuit having at least one isolation element; a digital to analog circuit having an analog output connected to the isolation barrier and an input for receiving an input digital signal to be communicated across the isolation barrier; and an analog to digital circuit having an input coupled to the analog output of the isolation barrier circuit for providing a digital output signal.

Isolation system with analog communication across an isolation barrier

An electronic device, such as a microprocessor, with a timing circuit. The timing circuit contains a phase locked loop that, during a first interval, checks whether a control signal in the phase locked loop is between a maximum allowed value and a minimum allowed value. When the control signal in the phase locked loop is above a maximum allowed value or below a minimum allowed value, the control circuit disables the phase locked loop for a second interval. When the control signal in the phase locked loop is below a maximum allowed value and above a minimum allowed value, the timing circuit indicates that the output of the phase locked loop is stable.

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Norwood, MA, United States of America

Daniel Boyko