Tahoe Research, Ltd.

Daniel B Aubertine

Jack T Kavalieros

Tahir Ghani

Willy Rachmady

Anand S Murthy

Glenn A Glass

Karthik Jambunathan

Subhash M Joshi

Gaurav Thareja

Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems within the same integrated circuit die. In accordance with one example embodiment, sacrificial fins are removed and replaced with custom semiconductor material of arbitrary composition and strain suitable for a given application. In one such case, each of a first set of the sacrificial fins is recessed or otherwise removed and replaced with a p-type material, and each of a second set of the sacrificial fins is recessed or otherwise removed and replaced with an n-type material. The p-type material can be completely independent of the process for the n-type material, and vice-versa. Numerous other circuit configurations and device variations are enabled using the techniques provided herein.

Self-aligned 3-D epitaxial structures for MOS device fabrication

Growing community of inventors

North Plains, OR, United States of America

Daniel B Aubertine