At&t Bell Laboratories

At+t Corp.

Globespan Technologies, Inc.

Daniel Amrany

Cecil William Farrow

Jin-Der Wang

Michael David Rauchwerk

Apparatus that realizes a substantial advantage by employing implied interleaving to create a systematic interleaver, that can result in a superior block error rate compared to the current data interleaving techniques in which uncorrected error bursts are distributed by the deinterleaver. The disclosed principles lead to a embodiments that essentially eliminate transmitter memory regardless of the interleaving approach employed. By way of example, block interleaving (regular or random), convolutional interleaving (regular and random) and product interleaving approaches are described. In implied interleaving, all incoming data is treated as if it is pre-interleaved and transmitted directly to its destination without alteration to its sequence, and essentially without delay. Concurrently with the transmission of the data, the data is applied to apparatus that treats the data as if it had been interleaved in accordance with a selected interleaving approach and, in accordance with such treatment, redundant symbols are generated and inserted into the transmitted data stream. At the receiver, the incoming data is delayed, corrected, and the information symbols in the incoming data are delivered to the user, corrected as necessary, in the same order as the information symbols arrived at the receiver.

Implied interleaving a family of systematic interleavers and

Implied interleaving, a family of systematic interleavers and

A self-synchronizing scrambler/descrambler arrangement operates in two modes. In the first, or start-up mode, predetermined data is coupled to the scrambler and transmitted to the descrambler. This data is used to 'seed', i.e., load, storage devices in the scrambler and descrambler with the same information. After a predetermined time interval, the start-up mode is terminated, and the scrambler and descrambler each operate in a steady-state mode. In this mode, the information loaded in the scrambler and descrambler devices are used to form the scrambler and descrambler key signals. Advantageously, in the steady-state mode, the occurrence of transmission errors does not effect the contents of the storage devices in the scrambler and descrambler. Hence, the prior art problem of error multiplication is avoided. In applications where a number of coded and multiplexed data channels are communicated over the communications channel linking the scrambler and descrambler, this approach allows the use of a single scrambler/descrambler without degrading the coding benefits.

Self-synchronizing scrambler/descrambler without error multiplication

A high-speed convolutional decoder is constructed by performing the transition, or branch, metric calculations in reference to a subset of a constellation, which comprises a plurality of subsets. In addition, any subset can be chosen as the reference subset through the use of 'modulo decoding.' In a modulo decoder, the constellation space is folded into a modulo set area that is centered around the arbitrarily chosen reference subset. The branch, or transition, metrics are calculated within the modulo set area. As a result, the branch metric computations are only performed on a small area of the signal space, with the result that only one error is extracted, the branch metrics are easily computed, and one slicing is performed--thus reducing overall computation time.

Modulo decoder

A signal dispersion cancellation structure receives incoming signal samples at an incoming rate, stores these samples in a first memory and then writes these samples at a submultiple of the incoming rate into a plurality of second memories. Each second memory is associated with a finite impulse response (FIR) filter and the second memory samples are coupled to the associated FIR filter at the incoming rate. Advantageously, apparatus is also provided which enables any sample in a second memory to be provided to the associated FIR filter and outputted therefrom at a time related to the position of any signal dispersion.

Technique utilizing signal storing devices for cancelling signal

A high-speed digital filter with a large dynamic range is constructed by operating two low-resolution filters in parallel, which is referred to as an 'overlap' mode of operation. In this overlap mode of operation, both low-resolution adaptive filters operate on the input data simultaneously, however, the characteristics of both filters are controlled so that one filter performs a coarse level of filtering, while the other filter performs a finer level of filtering and also removes any errors introduced by the first filter. Some application examples include echo canceling, equalization, and deghosting filters.

High resolution filtering using low resolution processors

The present invention addresses a timing synchronization problem which arises in tandem modem operation when a single codec strobed by a common sample clock is used for A/D and D/A signal conversion in a modem. Tandem modem operation is defined as a system application when two modems have their RS-232 interfaces directly connected to one another. In accordance with the present invention, a digital interpolator connected to the A/D converter in the modem effectively alters the timing phase of the A/D converter in response to first and second control signals. The first control signal is generated in response to an externally supplied clock and an internal modem clock and is representative of any perturbations in the externally supplied clock with respect to the internal modem clock. The second control signal is generated in response to digital signals derived from the incoming analog signal from a remote modem and is representative of any residual asynchronism between the transmit sample clock of the remote modem and the modem's transmit sample clock after alteration by the digital interpolator in response to the first control signal alone.

Timing recovery scheme for a transceiver using a single sample clock

A rational rate generator circuit is disclosed where the output signal frequency, f.sub.o, is rationally related to the input signal frequency, f.sub.i, by: f.sub.o =f.sub.i (P/Q). This rational rate generator is capable of a high-resolution output, where the resolution is only limited by the value of the integers P and Q, with P&lt;Q.

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Wayside, NJ, United States of America

Daniel Amrany