Motorola Corporation

General Instrument Corporation

Other

Motorola Solutions, Inc.

Daniel Alan Linzmeier

Sek M Chai

Malcolm Ryle Dwyer

Nikos Bellas

Ruei-Sung Lin

Kevin L Kloker

Zhiyuan Li

Erica M Lau

Charles Philipp Binzel

Robert Michael Johnson, Jr

Bruce A Augustine

Robert J Bero

Russell Mareachen

Nikolaos Bellas

Timothy M McCune

Edward J Yurchik

Nikolas Bellas

A method and apparatus for image processing a lens-distorted image (e.g., a fisheye image) is provided. The method includes partitioning coordinate points in a selected output image into tiles. The output image is an undistorted rendition of a subset of the lens-distorted image. Coordinate points on a border of the tiles in the output image are selected. For each tile, coordinate points in the lens-distorted image corresponding to each selected coordinate point in the output image are calculated. In addition, for each tile, a bounding box on the lens-distorted image is selected. The bounding box includes the calculated coordinates in the lens-distorted image. The bounding boxes are expanded so that they encompass all coordinate points in the lens-distorted image that map to all coordinate points in their respective corresponding tiles. Output pixel values are generated for each tile from pixel values in their corresponding expanded bounding boxes.

Method and apparatus for transforming a non-linear lens-distorted image

A method, apparatus, and electronic device for audio-video conferencing are disclosed. A memory may store an initial historical configuration parameter representation of an initial historical configuration parameter for a set of historical video data. A processor may determine a primary initial configuration parameter based on the initial historical configuration parameter representation. An audio-video capture mechanism may capture a current set of video data using the primary initial configuration parameter. An audio input may receive an audio trigger. A configuration control mechanism may switch automatically between the primary initial configuration parameter and a primary subsequent configuration parameter based on the audio trigger.

Audio visual tracking with established environmental regions

A specification of a configurable processor is generated by generating (1) specifications of first and second stream memory interfaces to be operable to access data in accordance with first and second stream descriptors, and (2) a specification of an interim data storage device (buffer) to be accessed by the first and second stream memory interfaces and to be operable to receive data from a first computational module via the first stream memory interface and to transfer data to a second computational module via the second stream memory interface. The specifications are output and may be used to configure a configurable processor.

Method and apparatus for configuring buffers for streaming data transfer

A streaming data interface device () of a streaming processing system () is automatically generated by selecting a set of circuit parameters () consistent with a set of circuit constraints and generating () a representation of a candidate memory interface device based upon a set of stream descriptors. The candidate streaming data interface device is evaluated () with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output () if the candidate memory interface device satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate memory interface devices.

Automatic generation of streaming data interface circuit

In one embodiment, a subset of a set of streaming kernels of an application is selected for implementation on a reconfigurable processor. The streaming kernels are selected by first forming a stream flow graph of the application by parsing a program of instructions of the application, the stream flow graph having kernel nodes and edges, and determining benefit and cost values for each kernel node in the stream flow graph. Next, a subset of the kernel nodes that maximizes a weighted sum of the benefits values is selected, subject to a constraint that the sum of cost values is not greater than a prescribed value for the reconfigurable processor.

Streaming kernel selection for reconfigurable processor

Bus transactions in a memory controller are scheduled by storing a set of configuration parameters that define a bus scheduling policy, generating values of a set of dynamic cost functions for each bus transaction, ordering the bus transactions in accordance with the bus scheduling policy to produce ordered bus transactions and generating a memory transaction that is derived from the ordered bus transactions. The memory controller includes one or more control registers for storing the set of configuration parameters, a bus interface operable to capture bus transactions from applications, a set of buffers operable to store the bus transactions and the set of dynamic cost functions and one or more registers operable to store the statistical data and a cost policy. The memory controller selects the order of the bus transactions based on an arbitration and selection policy and generates memory transactions to an external memory.

Dynamic access scheduling memory controller

A streaming processor circuit of a processing system is automatically generated by selecting a set of circuit parameters consistent with a set of circuit constraints and generating a representation of a candidate streaming processor circuit based upon the set of circuit parameters to execute one or more iterations of a computation specified by a streaming data flow graph. The candidate streaming processor circuit is evaluated with respect to one or more quality metrics and the representation of the candidate streaming processor circuit is output if the candidate streaming processor circuit satisfies a set of processing system constraints and is better in at least one of the one or more quality metrics than other candidate streaming processor circuits.

Automatic generation of a streaming processor circuit

A display apparatus, a display controller, and a method for optimizing a displayed image for use in an electronic devicecomprising a displayfor presenting a visual image, a processorfor determining the intensity of a backlightused for illuminating the displayand a controllerthat optimizes the visual image corresponding to the intensity of the backlightare described. As the intensity of the backlightis reduced, the brightness of the pixelsis increased to compensate the image when, for example, the backlight intensity is reduced to save power. The method and apparatus are also described for compensating for uneven backlightconditions.

Method and apparatus for image optimization in backlit displays

A serial arbitration system utilizes an arbitration token containing a start bit, a request bit, a set of priority bits, and an error detection bit. The arbitration token is sent to each of the other processors (20, 21, 22) and is used to arbitrate control of a shared bus (38). A processor indicates that it is the master (20) by setting the start bit (120). It enters an arbitration by setting the request bit (124). The set of priority bits (134) contains a binary priority value encoded in bit major order. This format allows an optimized parallel comparison (128, 130) of the priority values for each of the requesting processors a bit at a time. Finally, processors drop out of the arbitration upon detecting (136) a parity error in an arbitration token received from another processor.

Fault tolerant serial arbitration system

A serial arbitration system for arbitration between multiple processors (20, 21, 22) in a low power system has an arbitration line driven by each of the processors and received by each of the other processors. The arbitration lines (30, 31, 32) are coupled to arbitration ports (60, 61, 62, 63, 64) on each processor (20, 21, 22) numbered from zero for the driven arbitration port (60). Each of the processors (20, 21, 22) has a processor ID number, with a master processor (20) having ID zero. The arbitration line (30) driven by the master processor (20) is coupled to each other processor (21, 22) on the arbitration port (61', 62') numbered equal to the processor ID of that other processor (21, 22). The driven arbitration lines (31, 32) from the other processors (21, 22) are coupled to the arbitration ports (61, 62) on the master processor (20) corresponding to the processor ID of the driving processor (21, 22). Arbitration ports (63, 64) on the master processor (20) not driven by another processor (21, 22) are coupled to its arbitration line (30), while the remaining ports (63', 64') on the other processors (21, 22) are coupled to ground.

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Wheeling, IL, United States of America

Daniel Alan Linzmeier