Centre Suisse D'electronique Et De Microtechnique Sa

Daniel Aebischer

A circuit that includes a series arrangement of a capacitive element (C) and an active component (M10) forming an equivalent resistor. A DC current source (120 is connected to the active component, and a transistor (M11, 11) is provided for altering the conductance of the active component and fixing the mean level of a AC voltage (U.sub.ac). Such a voltage is applied to the terminals of the series arrangement, and the biased voltage having the desired mean level (U.sub.out) is tapped off the node (10) between the capacitive element (C) and the active component. A capacitive voltage divider (13) is also provided for modulating the DC current (i) passing through the active component (M10), with a fraction of the AC voltage to be biased. The circuit is particularly applicable to the determination of the mean level of the voltage produced by a quartz oscillator.

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Neuchatel, Switzerland

Daniel Aebischer