Texas Instruments Corporation

Freescale Semiconductor,inc.

Daniel A Mavencamp

Siew Kuok Hoon

Jairo Daniel Olivares

Karthik Nandimandalam Venkata

Lawrence Edwin Connell

Pallab Midya

Patrick Lee Rakers

William J Roeckner

Mustapha El Markhi

Suheng Chen

Rohit Bhan

Ronnie A Bean

Bradley C Stewart

Thomas Vermeer

Wang Li

Abdelhalim Alsharqawi

Steve Martindell

Dal Yihong

Tim Colvin

A device includes a battery current sense circuit configured to generate a battery current feedback voltage based on a current provided to a battery, a current regulation feedback loop configured to regulate the current provided to the battery based on the battery current feedback voltage and a configurable battery current reference voltage, and a precharge regulation feedback loop configured to regulate the current provided to the battery based on the battery current feedback voltage and a configurable precharge reference voltage. The device also includes a processor configured to set the battery current reference voltage to a first value and set the precharge current reference voltage to a second value. The first value is less than the second value during a transition state.

Current protection for battery charger

Aspects of the present disclosure provide for circuit. In at least some examples, the circuit includes a controller, a current source, a switch, and a digital-to-analog converter (DAC). The controller includes an analog-to-digital converter (ADC) having an input and an output, a first register, and a second register coupled to the output of the ADC. The switch is coupled between an output of the current source and a first node and has a control terminal coupled to the controller. The first node is coupled to the input of the ADC and is configured to couple to a resistor. The DAC has an input coupled to the controller and an output configured to couple to a battery.

Charging current limit circuit

A system that can include a detector that can monitor a voltage at an input of a transistor device over a period of time and provide a signal having a value representative of a capacitance between the input and an output of the transistor device. The system can further include a driver that can have a programmable drive strength and be coupled to input of the transistor device to drive the transistor device at the input thereof. The system can further include a controller that can configure the driver based on the signal to drive the transistor device with a corresponding drive strength.

Adjusting drive strength for driving transistor device

Systems and methods for bit stuffing pulse width modulation are provided. Example embodiments of the systems and methods of bit stuffing pulse width modulation disclosed herein may allow for a significant reduction in the size of the bootstrap capacitor while giving up only a small percentage of output drive, and reduce die space. Included in such systems and methods is the ability to digitally detect inactivity on the PMW signals for a class D power amplifier, and to digitally insert small charge pulses at a fairly low repetition rate relative to the normal switching frequency. The low repetition rate may preserve the maximum output power while still allowing enough charge to transfer to the bootstrap capacitor.

Systems and methods of bit stuffing pulse width modulation

Power amplifiers with reduced idle currents are described. In some examples, a power amplifier includes a driver configured to generate a control signal based on an input signal. The power amplifier also includes a first output transistor configured to selectively provide an output signal via an output channel that has a resistance based on the control signal, and a channel adjuster configured to generate several digital signals based on the control signal. A composite switch, which includes several segment transistors, is included to selectively increase or decrease the output channel resistance based on the digital signals.

Methods and apparatus to reduce idle current in power amplifiers

A closed loop audio amplifier system and method of powering up/down the system without producing audible artifacts are provided. During power up, a prebias voltage is provided to each output connected to a speaker to increase the voltage to a nominal output level. High impedance switches are then driven at a 50% duty cycle. Feedback from the output is supplied to a servo, which is enabled to fine tune the output voltage. Low impedance switches are then driven at a 50% duty cycle at a quarter cycle timing. The order of the feedback loop depends on which of the high or low impedance switches are driven. The prebias voltage is then removed before audio signals to be amplified are supplied to the system. Timing of driving of the switches is programmable. To power down, essentially the reverse sequence is provided.

Quiet power up and power down of a digital audio amplifier

Provided is a method ( ) and audio circuit ( ) for reducing popping noise in a load ( ) connected to the audio circuit, especially during audio circuit start-up. The method applies a time varying voltage ( ) to the load that has a smooth, S-shaped curve when plotted over time. The device include an integrated circuit (IC) set as a channel block ( ), a load connected between the channel block and ground, a bypass control ( ) connected to the channel block for producing a controlled ground reference voltage having an S-shaped curve to the channel block, a shunt control ( ) controlling the voltage delivered across the load, and a ground capacitor ( ) coupled between the bypass control and ground. The channel block typically includes an amplifier which supplies the output voltage across the load. The bypass circuit generally includes a bypass generator and a transistor selectively providing a charge to the ground capacitor.

Three-step ramped reference to reduce popping noises on audio circuit

An improved bias network for reducing cross-over distortion in a device having complementary p-MOS and n-MOS power transistors includes complementary helper transistors coupled to power transistors for discharging currents while the power transistors are biased in sub-threshold regions of operation. The bias network further includes complementary resistors coupled to the power transistors for biasing the power transistors within saturation regions of operation and for biasing the helper transistors within saturation regions of operation, and complementary feedback circuits connected to the power transistors and operating in conjunction with the resistors for biasing the helper transistors within the saturation regions of operation. Preferably, each of the power transistors are biased into the saturation regions by gate voltage swings of no more than 200 millivolts from the sub-threshold region.

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Brandon, MS, United States of America

Daniel A Mavencamp