Intel Corporation

Daniel A Manseau

Anshuman Thakur

Linda J Rankin

Hemal Vinodchandra Shah

Nitin Y Borkar

Robert W Cone

Suvansh Krishan Kapur

Mark W Wunderlich

Frank Verhoorn

Linda C Ernst

Ramesh S Krishnan

Joseph Bonasera

Nicholas A Colman

Provided are techniques for processing a data segment by stripping a header from a transport layer segment, performing protocol data unit detection to determine data for a protocol segment that is part of the transport layer segment data, and performing marker validation and stripping.

Processing receive protocol data units

Input/Output (I/O) protocol operations such as iSCSI protocol operations may be selectively offloaded to an I/O protocol offload device, or retained by a host driver software. In one embodiment, iSCSI data transfer functions are offloaded to an offload device while session and connection establishing and maintenance operations are retained by host driver software. Other features are described and claimed.

Offloading data path functions

According to one embodiment, a computer system is disclosed. The computer system comprises a main memory; and a chip set coupled to the main memory. The chip set comprises a transaction memory, a first bank controller and a second bank controller coupled to the transaction memory. The first bank controller stores transaction data to be transmitted to a first bank of main memory within the transaction memory according to a first linked list. The second bank controller stores transaction data to be transmitted to a second bank of main memory within the transaction memory according to a second linked list.

Method and apparatus for managing out of order memory transactions

A method and apparatus for providing highly programmable memory mapping and improved interleaving includes a system address chip that maps a received memory transaction address to an intermediate address for accessing a memory array having at least one individually addressable memory row. During the translation the memory array is logically partitioned into a plurality of individually addressable memory blocks such that each of said memory blocks are interleavingly accessible independent of how said memory array is populated. The apparatus includes logic to generate at least a portion of the intermediate address by combining selected bits of the transaction address with selected bits of a programmed block address based in part upon the received transaction address.

Method and apparatus for providing highly programmable memory mapping and improved interleaving

A massively parallel data processing system is disclosed. This data processing system includes a plurality of nodes, with each node having at least one processor, a memory for storing data, a processor bus that couples the processor to the memory, and a remote memory access controller coupled to the processor bus. The remote memory access controller detects and queues processor requests for remote memory, processes and packages the processor requests into request packets, forwards the request packets to the network through a router that corresponds to that node, receives and queues request packets received from the network, recovers the memory request from the request packet, manipulates local memory in accordance with the request, generates an appropriate response packet acceptable to the network and forwards the response packet to the requesting node.

Growing community of inventors

Portland, OR, United States of America

Daniel A Manseau