Lsi Logic Corporation

Lsi Logic Corporatino

Daniel A Luthi

Advait Madhav Mogre

Dojun Rhee

Ravi Bhaskaran

Dariush Dabiri

Christopher R Keate

Dariush Daribi

A method and system for compensating for code invariancies in a digital communication receiver is performed on demodulated signal data. A pre-Viterbi invariancy compensation is performed on the demodulated signal data to reverse a selected one of a number of possible transformations to create compensated signal data. The compensated signal data is then depunctured. The depunctured data is then decoded. An encoder encodes the decoded data. The encoded data and the depunctured data are then compared to determine equivalence. The pre-Viterbi invariancy compensation is performed to reverse a different one of the number of possible transformations to create the compensated signal data when the encoded data and the depunctured data are determined not to be equivalent. A post-Viterbi invariancy compensation is then performed on the decoded data to produce a set of compensated outputs. Thus, the post-Viterbi invariancy compensation reverses each one of the number of possible transformations on the decoded data. An output is then selected from between the set of compensated outputs and the decoded data in response to detection of a sync byte.

Method and system for automatic invariancy compensation in digital

This invention concerns a novel Viterbi decoding apparatus and method in which a survivor path unit (SPU) implements the traceback method with a RAM which stores path information in a manner which allows fast read access without requiring physical partitioning of the RAM. This results in an implementation that requires less chip area than conventional solutions.

Area-efficient surviving paths unit for Viterbi decoders

The present invention concerns a DBS receiver which serves to combine the functions of variable rate demodulation, convolutional decoding, de-interleaving and block decoding. The demodulation stage includes a novel circuit for clock synchronization. By combining the functions of these components this device provides a higher level of utility as measured in terms of reliability, simplicity, flexibility, cost effectiveness, and integration of board layout while maintaining optimum-quality signal processing.

Single-chip DBS receiver

A communications receiver system is presented for detecting burst errors and providing erasure information to a block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, the receiver includes a demodulator which includes circuitry to detect error bursts in the received symbol sequence. Once detected, the locations of symbols in error are marked in the form of erasure flags. An error correction decoder is then able to correct up to twice as many errors with the additional information provided by the erasure flags.

Non-equalized digital receiver using block decoding with erasure and

A video device is provided having a more efficient Reed-Solomon decode methodology. The Reed-Solomon decoder advantageously receives pre-indentified error locations and, given those locations, focuses entirely upon correcting (as opposed to detecting) erroneous symbols at those locations. A noise detector is used to identify erroneous symbol intervals, and forwards information signifying erroneous symbol locations or erases symbols within those locations. The detected error locations are forwarded to the Reed-Solomon decoder which then adds (or subtracts) correction quantities to symbols within those locations. Given pre-identified error locations, the Reed-Solomon decoder can correct double the number of corrupted symbols. The decoder, herein provided, therefore proves beneficial in high speed decoding of video signals sent from a video device having forward error correction.

Video device with reed-solomon erasure decoder and method thereof

A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Digital receiver using a concatenated decoder with error and erasure

A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder (outer decoder), thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

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San Jose, CA, United States of America

Daniel A Luthi