Texas Instruments Corporation

Daniel A King

Vadim Valerievich Ivanov

Harish Venkataraman

Gary Franklin Chard

Susan A Curtis

Scott Adam Morrison

A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage.

Power management system and method with adaptive noise control

A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.

Fast startup algorithm for low noise power management

An apparatus is provided. The apparatus includes an analog timing controller and a digital state machine. An input circuit in the digital state machine is configured to receive a plurality of analog input signals, and an analog event circuit is coupled to the analog timing circuit, the glitch filter, and the input circuit. The analog event circuit and input circuit are configured to generate a composite event signal from the analog input signals and by using the analog timing circuit. The glitch filter is configured to receive the composite event signal. A clock generator also is coupled to the glitch filter, wherein the clock generator is configured to generate an aperiodic clock signal. The aperiodic clock signal is configured to be a synchronous clock signal for the digital state machine.

Synchronous state machine with an aperiodic clock

A comparator () includes a first input transistor (M) having a drain coupled to a gate and drain of a first diode-connected transistor (M) and a gate of a first current mirror output transistor (M), and a second input transistor (M) having a drain coupled to a gate and drain of a second diode-connected transistor (M) and a gate of a second current mirror output transistor (M). Sources of the first and second current mirror output transistors are connected to a supply voltage (V). Gates of the first and second input transistors are coupled to first (V) and second (V) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M,M) is coupled to the drains of the first and second current mirror output transistors.

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Daniel A King