Cavium, Inc.

Cavium Networks, Inc.

Marvell Semiconductor, Inc.

Oavium Networks, Inc.

Daniel A Katz

Richard Eugene Kessler

Wilson Parkhurst Snyder, Ii

Michael S Bertone

Thomas Frederick Hummel

Robert A Sanzone

Shahe Hagop Krakirian

Paul G Scrobohaci

Gregg Alan Bouchard

Muhammad Raghib Hussain

Faisal Masood

Philip H Dickinson

Imran Badr

Varada Ramesh Ogale

Thucydides Xanthopoulos

Srikanth Gummalla

A packet parsing engine comprises a DMEM configured to store packet data; one or more registers configured to store parsing instructions or parse results; and one or more arithmetic logic units configured to parse the packet data based on the parsing instructions and to derive the parse results. The engine may be one engine of a plurality of engines configured to access a shared memory, and the engine may be configured to receive data from the shared memory or to send data to the shared memory. The DMEM may be divided into subsections, and at least one of the one or more registers may be divided into subsections, and the subsections may be configured such that while a DMEM subsection and its corresponding register subsection is parsing packet data for a first packet, one or more other subsections load packed data or unload parse results for a second packet.

Packet parsing engine

In an embodiment an interface unit includes a transmit pipeline configured to transmit egress data, and a receive pipeline configured to receive ingress data. At least one of the transmit pipeline and the receive pipeline being may be configured to provide shared resources to a plurality of ports. The shared resources may include at least one of a data path resource and a control logic resource.

Multiple ethernet ports and port types using a shared data path

A method for parsing network packets via one or more clusters configured to parse network packets comprises receiving one or more packets to be parsed; determining a candidate cluster of the one or more clusters for parsing the one or more packets; transmitting the one or more packets to the candidate cluster; launching the candidate cluster to parse the one or more packets when a launch condition is met; and receiving parse results for the one or more packets from the candidate cluster. The launch condition may be met after transmitting the one or more packets meets a fraction of a parsing capacity of the candidate cluster. The fraction may be one such that the transmitting the one or more packets meets a parsing capacity of the candidate cluster. The launch condition may also be met when a time elapsed since a previous cluster was launched reaches a delay limit.

Methods and systems for distribution of packets among parsing clusters

In one embodiment, a system includes a packet reception unit. The packet reception unit is configured to receive a packet, create a header indicating scheduling of the packet in a plurality of cores and concatenate the header and the packet. The header is based on the content of the packet. In one embodiment, a system includes a transmit silo configured to store a multiple fragments of a packet, the fragments having been sent to a destination and the transmit silo having not received an acknowledgement of receipt of the fragments from the destination. The system further includes a restriction verifier coupled with the transmit silo. The restriction verifier is configured to receive the fragments and determine whether the fragments can be sent and stored in the transmit silo.

Messaging with flexible transmit ordering

Methods and systems are provided for operating a SIMD packet parsing cluster, wherein the cluster includes a plurality of M packet parsing engines 1 to M, and the cluster further includes a shared memory and an instruction memory storing a plurality of instructions to be performed by each of the engines, and wherein the instructions include one or more memory accessing instructions that require accessing the shared memory. The method comprises transmitting the instructions to the engines for instructions to be executed by the engines; for each of the engines 2 to M, delaying execution of each of the memory accessing instructions by a delay time compared to a previous engine; and each one of the engines performing one of the memory accessing instructions at a time that the other engines are not performing one of the memory accessing instructions.

Methods and systems for resource management in a single instruction multiple data packet parsing cluster

In one embodiment, a system includes reassembly stores configured to store a fragment of a packet in a particular reassembly store corresponding with the packet, and when the particular reassembly store contains fragments of the packet representing the packet as a whole, forward the packet to a plurality of cores. The system further includes a packet reception unit configured to store the fragment in one of a plurality of memories within the reassembly stores, and, when the one of the plurality of memories is filled, copy the at least one fragment to a memory external to the packet reception unit.

In a network processor, a 'port-kind' identifier (ID) is assigned to each port. Parsing circuitry employs the port-kind ID to select the configuration information associate with a received packet. The port kind ID can also be stored at a data structure presented to software, along with a larger port number (indicating an interface and/or channel). Based on the port kind ID and extracted information about the packet, a backpressure ID is calculated for the packet. The backpressure ID is implemented to assign a priority to the packet, as well as determine whether a traffic threshold is exceeded, thereby enabling a backpressure signal to limit packet traffic associated with the particular backpressure ID.

Packet priority in a network processor

A network transport layer accelerator accelerates processing of packets so that packets can be forwarded at wire-speed. To accelerate processing of packets, the accelerator performs pre-processing on a network transport layer header encapsulated in a packet for a connection and performs in-line network transport layer checksum insertion prior to transmitting a packet. A timer unit in the accelerator schedules processing of the received packets. The accelerator also includes a free pool allocator which manages buffers for storing the received packets and a packet order unit which synchronizes processing of received packets for a same connection.

TCP engine

A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.

Growing community of inventors

Holliston, MA, United States of America

Daniel A Katz