Apple Inc.

Daniel A Jimenez

Tyler J Huberty

Henry A Pellerin

A cache memory supports a plurality of insertion/promotion vectors (IPVs) and a replacement control circuit configured to update replacement data for the cache memory based on the plurality of IPVs. In one embodiment, the IPV is selected for a given request based a criticality status of a cache line accessed by the given request. For example, cache lines deemed important or critical for performance reasons may be replaced less frequently via a first IPV, while non-critical cache lines are replaced more frequently via a second IPV.

Growing community of inventors

College Station, TX, United States of America

Daniel A Jimenez